Compiler





Agere Systems Network Processor Design
The value seen in FPGA prototyping for emulating ASIC designs is recognized across a growing spectrum of design applications. Dave Brown and Roger Bailey, from Agere Systems, explain how the use of a design flow based around Synopsys’ Design Compiler® FPGA (DC FPGA) solution enabled the successful development of a complex network processing design.

Simplifying the management of traffic flow under demanding network conditions requires the use of increasingly complex network processor chips. To stay at the top of this highly competitive market, Agere Systems’ latest 210-million transistor design offers vastly improved performance and enhanced capabilities over previous network processor generations. However, both of these design constraints must be met at minimal cost to the system providers.

The needs of Agere’s markets are constantly evolving, something that Dave Brown of Agere is quick to acknowledge: “There’s enough competition out there for people to go elsewhere if you don’t have exactly what they need.” In an industry that usually offers high-performance chips with fixed ASIC functionality, or full programmability at the expense of speed, Agere’s chip offers the best of both worlds. Brown’s colleague, Roger Bailey, elaborates: “We integrated a traffic manager around the classification engine, which creates flexibility for future implementations. This provides a programmable engine that also has the capabilities of hardwired functions that can be called upon when we want the network to perform quickly.”

Cost Drives Economic Design Approach
A primary concern for network processor design is cost. With service providers increasingly concerned about pricing pressures on long distance phone rates and escalating expenses, Agere was keen to provide a solution to the ‘box makers’ at a reduced cost. Using just one chip instead of three reduced the cost by half for low end solution users, who also benefit from having a huge 2.7MB of on-chip memory available. For customers requiring a high-end solution, off-chip memory can be easily added to enable even higher performance.

“Service providers have installed fibre everywhere in the last ten years,” Bailey says. “Enabling that fibre cost-effectively, through bandwidth and function, is another big challenge. The enhanced new feature set enables the service provider to have that equipment installed, deployed, and live for a number of years. That’s what we bring to the table: in addition to all the established protocols, we support interfacing to standards such as Sonet, Ethernet, MPLS and others.”

With customers demanding lower prices, Agere realised the need for a higher yield, something which is reflected in the economical design of the chip. “You have to pay special attention to chip design in the 0.13-micron technologies where the variability of the process is unpredictable,” Bailey says. “Method of assembly, and width and spacing of metal layers, is germane to the bottom line cost of the part. We’re always scouring the landscape for the most suitable design methodology.”

Extreme Design Challenges
Customer demand for increased performance was met by developing a 5Gbit design, doubling the data rate over the previous generation to enable different protocol data unit (PDU) sizes to be handled. Designing the memory bandwidth into the appropriate areas of the chip was no simple feat. It required the use of fast cycle RAM technology, the newest available type of memory architecture.

Agere Figure 1
Figure 1: The building blocks of a PayloadPlus network processor

Another challenge involved getting eleven memory interfaces within the design to run at a target frequency of 266MHz. Sophisticated design and considerable effort were required to lay the interfaces out across 1413 pins, including 953 signal pins. “It’s hard enough to get the DDR interface to run correctly,” notes Dave Brown. “Not to mention doing it eleven times. I have friends at other companies who are surprised that we managed to complete the task at all.”

Agere used the Synopsys tool suite for this task, as they did for most of the implementation flow. “We start with Design Compiler and use Power Compiler, go to Astro for routing, Hercules for checking, Star-RCXT for extraction, and Primetime for timing,” Bailey says.

The Agere design team recognizes that in a complex, control-dominated design, achieving the intended functionality is a central challenge that requires a lot of work. “In our design methodology, we use FPGA emulation as a precursor to silicon,” Bailey comments. “That is where Synopsys has helped us a great deal. We worked with them early on to develop and enhance their DC FPGA tool. It really paid off for us, in terms of the gate count, frequency, runtime and turnaround time that the tool gives us.”

Agere appreciates the importance of emulating the chip before building it – a necessary measure, considering the number of gates and functions involved. “The testing process involves breaking the design into pieces, fitting it into a number of FPGAs, getting it on a board, and hitting it with some real world data patterns and applications. We give ourselves some margin to account for feature creeps.”

Synopsys developed its tools to meet Agere’s requirements. “We used the DC FPGA tool very early in a beta program” says Brown. “Synopsys took our design and used it to improve the beta version of DC FPGA. To our surprise, we were able to fit more of that logic into our FPGAs as the tool got better and better, so eventually we validated what we were going to build in silicon.”

DC FPGA ultimately enabled Agere to map more and more functions into a fixed set of programmable chips to validate the design. They were able to take new features and architectural ideas and incorporate them into the prototype so that the performance could be checked and the ASIC development validated with real data. Critically, DC FPGA enabled the design team to keep one source RTL to use for both the ASIC and FPGA.

“The physical design was quite advanced when we got to the point where we could start testing performance in our FPGA platform, so we didn’t want to kill the physical design schedule by altering things drastically,” says Brown. When we found we weren’t meeting our performance criteria, together with the architects we determined what various schedule and design options would cost. We spent an intense month looking for solutions, and finally achieved a result that was acceptable.”

Anticipating the Future
While the Agere design team plans to be focused on bandwidth and the wireline and wireless access market for the next several years, it is difficult for them to speculate further with technology developing at such a fast pace. “The network is evolving in directions that we wouldn’t have anticipated a year ago,” says Bailey. “We will still provide network processors that offer robust, finely granulated traffic management, as well as are faster, more cost-effective, and that deliver greater function, flexibility and performance to our customers.”

Brown adds: “In one sense we are immersed in design, completely dedicated to what we’re trying to implement at any given time, but we regularly resurface to take a good look around and think about the future.”

On tool and vendor selection, Agere is clear. “It’s not just about the best point tool or flow – we look for willing suppliers to help us achieve our goals.” asserts Bailey. “Synopsys demonstrated exactly that attitude with DC FPGA. They were willing to come in, understand what we do, and chose to enhance their tool to that function, which was great - it’s a win-win deal.”

Technical Chip Specifications
  • 1413 pins
  • 953 signal pins
  • 210 million transistors
  • 11 memory interfaces (including DDR SRAM) run at 266 MHz
  • 0.13-micron technology
Key Tools in Agere’s Design Flow
  • Synthesis – Design Compiler®
  • FPGA Synthesis – DC FPGA
  • Simulation – VCS®
  • Static Timing Analysis – PrimeTime®
  • Physical optimization, placement and routing – Astro™
  • Physical verification – Hercules™
  • Parasitic extraction – Star-RCXT™

About Agere Systems
Agere Systems is a global leader in semiconductors for storage, wireless data, and public and enterprise networks. The company's chips and software power a broad range of computing and communications applications, from cell phones, PCs, PDAs, hard disk drives and gaming devices to the world’s most sophisticated wireless and wireline networks. Agere's customers include top manufacturers of consumer electronics, communications and computing equipment.

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"It's not just about the best point tool or flow – we look for willing industry leaders to help us achieve our goals."