Test Solutions for Deep Submicron
With Deep SubMicron processes, especially 90nm designs and below, the test game has changed – both in terms of design and measurement. T. W. Williams, Synopsys Fellow, describes the new issues for DSM test and how Synopsys is addressing these challenges with the latest tools in Galaxy Test.
An analysis of design tape out statistics clearly demonstrates that 90nm technology has truly arrived. In the summer of 2004, Synopsys’ own data suggested that over 220 designs targeting 90nm processes were underway, with 80 having taped out, and 51 of those exclusively using Synopsys back-end place and route solutions. An additional 16 used a combination of Synopsys and other tools. All of those figures will have increased substantially by now, comprising the thirty-odd 65nm designs that were underway (including the first to tape out – entirely with Synopsys tools), as well as a handful of 45nm designs.
The Old Rules Don’t Apply
What do 90nm design start figures have to do with test? Fundamentally, with deep submicron (DSM) designs of 90nm and below, test solutions have to be re-thought because the old rules don’t apply. The critical issue with sub-90nm processes is yield and yield loss is no longer primarily due to random defects as it was in the past. Today yield loss is the result of not only random defects but also printability problems and systematic defects e.g. signal integrity.
Yield (Total) = Yield (Random Defects) * Yield (Printability) * Yield (Systematic)
All of these yield factors worsen at 90nm and below, to compound the overall effect on the final chip yield.
Figure 1: Manufacturing Yield in DSM Processes
Source: IBS report
At fine process geometries it is far more cost-effective to utilize large on-chip memory. As a result, in future designs, the percentage of memory compared with logic is expected to increase substantially. The implications for test strategy are clear – without efficient memory BIST, MBIST, and memory self-repair mechanisms, overall yield will be catastrophically low.
With DSM technology, new fault models and testing mechanisms are required. For example, contact defects require at-speed delay testing, and metal defects require resistive shorts testing. Open vias, which are becoming more of a problem, also requiring delay tests. Large chips introduce relatively greater proportions of wiring, which means that wire-related faults (such as bridging) become more important in considering the test strategy.
Inevitably, the dramatic growth in design complexity has implications for the number of test vectors now required to test chips. More vectors imply that more time is required to test each device, with the consequent impact on cost. Because the old rules no longer apply, there is a need for a new approach to test.
Synopsys Galaxy Test Solution
Galaxy Test is a comprehensive test automation solution within the Galaxy Design Platform that offers designers of ASICs and SoCs the fastest path to test implementation, testability sign-off, high-quality manufacturing test and working silicon with lowest overall test cost.
Synopsys’ Galaxy Test Automation solution offers a comprehensive family of products for mainstream to high-performance semiconductor designs. The solution includes the advanced DFT Compiler, TetraMAX® ATPG and DFT Compiler SoCBIST products. The Galaxy Test Automation solution incorporates capabilities that enable designers to achieve DFT closure and sign off on the testability of their mainstream ASICs, as well as reduce test cost and time and data volume for their most complex designs. Galaxy Test offers a standards-based test automation solution for core-based design that speeds the creation, integration, and verification of test reuse-ready IP.
Figure 2: Galaxy Test Solution
DFT Compiler: Physically-aware DFT Synthesis
Design for Test must be addressed throughout the entire design flow. This requires test synthesis solutions for scan synthesis, boundary scan, memory BIST and scan compression.
DFT Compiler provides 1-Pass test synthesis, advanced RTL Test DRC and AutoFix features.
Recent enhancements to DFT Compiler include more efficient memory management which provides 2x faster runtime and 2x increased capacity over previous releases.
The introduction of physically-aware DFT optimization avoids scan hold-time violations and means that Galaxy 2004 with DFT Compiler provides the fastest path to DFT closure. Physically-aware DFT optimization ensures that scan chains are appropriately partitioned and ordered with respect to the physical layout. Timing-based Physical Ordering using DFT Compiler in conjunction with Physical Compiler enables rapid timing closure by taking a proactive approach to hold-time violations. With timing–based physical ordering the test designer can expect no hold-time violations. The alternative approach, using location-based physical ordering, can result in thousands of hold-time violations which have to be dealt with. These violations need to be dealt with by the designers after the design is complete and thus delaying the chip’s release. These problems are limited with Galaxy 2004.
TetraMAX® ATPG automatically generates high-quality manufacturing test vectors. TetraMAX is the only ATPG solution optimized for a wide range of test methodologies that is integrated with DFT Compiler, the leading test synthesis tool. The unparalleled ease-of-use and high performance provided by TetraMAX allows RTL designers to quickly create efficient, compact tests for even the most complex designs.
TetraMAX ATPG now includes advanced merging algorithms that require 2x fewer test patterns. At-speed test with on-chip clocking now provides fully-automated PLL support. Physically-aware fault models enable a complete flow for bridging faults, and accurate failure diagnostics generate greater than 95% coverage for all fault models
On large DSM devices, where increasingly, more silicon area is consumed by wires rather than transistors, there are relatively more manufacturing defects arising from bridging (wire-related) faults than from stuck-at (transistor-oriented) faults. TetraMAX® DSMTest enables the use of layout extraction information to now generate bridging fault tests. TetraMAX DSMTest enables testing for transition, bridging and path-delay faults.
DFT Compiler SoCBIST
SoCBIST is an add-on to DFT Compiler that enables designers to implement deterministic logic BIST (DBIST) test capabilities transparently in their designs without impacting the functional or timing requirements of the design. The DFT Compiler SoCBIST add-on reduces both test data volume and test time significantly, while obtaining the same high-fault coverage as full scan design. DFT Compiler SoCBIST provides a complete range of powerful BIST design rule checking (DRC), synthesis, integration, verification, and diagnostic capabilities. Fully integrated within the Synopsys physical synthesis design flows, this BIST solution is built on the industry’s leading test platforms, DFT Compiler and TetraMAX ATPG to ensure a dependable and easy-to-adopt DFT flow.
Figure 3: SoCBIST Test Vector Compression
Compared to traditional scan techniques, DFT Compiler SoCBIST ensures significant reductions in test data volume, tester application time and therefore cost of test, all with minimal impact on the existing design flow. At the same time DFT Compiler SoCBIST delivers predictable and high fault coverage.
Achieving testability in concert with power and timing is a key concern. During the design phase, Synopsys’ Galaxy Power tools perform dynamic power management with test in mind. Power Compiler, in particular, inserts clock-gating with appropriate test observability and controllability logic to preserve the test coverage and testability.
Additionally, power is of critical concern during physical testing - for example, when running at-speed vectors through the tester. The test patterns must not only meet the peak current specification of the tester, but also it is very important to reduce the switching activity of the vectors to reduce peak power and thus avoid spurious chip failures. Historically, in full-scan designs, the average power consumption for scan ATPG vectors is roughly about 3x of mission (normal, functional) mode. Recent design evaluations have revealed that scan patterns in some designs may consume almost 30x of peak power over its mission mode. Without caution, such a magnitude of difference in power consumption can easily lead to permanent damage to the device under test, or, at the very least, result in reliability failures due to electromigration.
Galaxy Power provides a low-power test pattern generation flow for higher shippable yield using PrimePower’s accurate peak power analysis in conjunction with Synopsys’ industry-leading TetraMAX.
Integrated with major ATE platforms
The Synopsys Galaxy Test Solution interfaces with all leading test hardware, including device testers from Agilent, Inovys, Advantest, Teradyne, Credence and Teseda.
Galaxy Test is a comprehensive test automation solution for unified RTL-to-manufacturing test. This unified solution eliminates costly iterations between design synthesis and test implementation and enables IC designers to achieve timing, area, power and DFT closure for the latest DSM designs. In addition, it provides comprehensive and easy-to-use design rule checking and validation features within SoCBIST, along with powerful BIST integration, verification, diagnostic and debug tools.
T. W. Williams has served as founder, chair and distinguished speaker for a number of IEEE and IEEE Computer Society events and technical committees. An accomplished writer and educator, Dr. Williams has contributed to numerous technical books and papers in the area of test, is an adjunct professor at the University of Colorado in Boulder, and has served as a guest professor and Robert Bosch Fellow at the Universitaet of Hannover in Hannover Germany (1985,1997). He was named an IEEE Fellow in 1988 for leadership and contributions in DFT, and in 1989 was co-awarded the IEEE Computer Society's prestigious W. Wallace McDowell Award for the development of level-sensitive scan test for solid-state logic circuits and for leadership in the area of DFT.
Prior to joining Synopsys, Dr. Williams was with IBM's Microelectronics Division in Boulder, Colorado, where he managed the VLSI Design for Testability group. He received a BSEE from Clarkson University, an MA in pure mathematics from the State University of New York at Binghamton, and a Ph.D. in electrical engineering from Colorado State University.
©2007 Synopsys, Inc. Synopsys and the Synopsys logo are registered trademarks of Synopsys, Inc. All other company and product names mentioned herein may be trademarks or registered trademarks of their respective owners and should be treated as such.