Next Generation Scan Synthesis
As chip designs become larger and new process technologies require more complex failure modes, the length of scan chains and the number of scan patterns required have increased dramatically. To maintain adequate fault coverage, test application time and test data volume have also escalated, which has driven up the cost of test. Rohit Kapur, Test Automation Scientist, and Kirk Brisacher, Director of Corporation Applications Engineering for Test Automation, explain how Synopsys’ new DFT Compiler MAX enables an enhanced Adaptive Scan architecture that offers a 10-50X reduction in test application time and test data volume.
DFT Compiler MAX extends the Synopsys 1-pass test synthesis solution, DFT Compiler, by enabling designers to implement test compression technology predictably without affecting the functional, timing, or power requirements of the design. Combined with the powerful Synopsys TetraMAX ATPG, DFT Compiler MAX provides a complete range of design rule checking (DRC), synthesis, integration, pattern generation, verification, and diagnostics capabilities.
Economics Drive IC Test Methodologies
Scan chain values currently dominate the total stimulus and observe values of the test patterns, which constitute the test data volume. With the limited availability of inputs and outputs as terminals for scan chains, the number of flip-flops per scan chain has increased dramatically. As a result, the time required to operate the scan chains, or the test application time, has increased to the extent that it is becoming uneconomic to employ scan test on complex designs. To understand the impact of shift time on test application time, consider the typical sequence involved in processing a single scan test pattern:
All these steps — excluding the shift operations in steps 2 and 7 — require one clock period on the tester. The shift operations, however, take as many clock periods as required by the longest scan chain. Optimizations (such as overlapping of scan operations of adjacent test patterns) still do not adequately influence the unwieldy test application time required by the scan operation.
The Synopsys patented new scan architecture – Adaptive Scan – offers a new approach to IC testing that provides a more efficient way to test digital logic. This new methodology enables the application of traditional scan test patterns, while reducing data storage requirements on the automated test equipment (ATE) and maintaining the quality of the test patterns. In addition, test patterns are applied to the device in significantly less time, which directly reduces the test cost of the manufactured ICs. By keeping the overall impact of testing in check, this technology lays the foundation for the next generation of IC test.
A New Methodology for Efficient Scan Testing
Fault detection requires that only a small percentage of stimulus and measure points of a design’s inputs, outputs, and scan elements be accessible for test. Prior to the rise of test data volume and test application time, the typical industry practice was to place random values in the remaining stimulus points of the pattern (logic X’s). Test compression technology creatively discovers alternatives for handling these randomly filled bits, which increases test data volume and test application time efficiency.
Test compression introduces logic in the scan path at scan-in and scan-out. Test data volume and test application time benefits are achieved by converting data from a small scan interface at the design boundary to a wide scan interface within the design. This approach enables significantly more scan chains in the design than allowed by its signal interface.
Because the goal of test compression is to increase the efficiency of scan testing, this new technology provides better results without losing the existing benefits of scan. Not every test compression technique is compatible with scan technology.
Simplicity is the most important feature of scan technology. Scan test is easy to understand, implement, and use. Because of this simplicity, scan has been incorporated successfully in design flows without disrupting important layout and timing convergence considerations. Even more importantly, the following features of scan test are now widely understood in the industry:
- Scan has “low” area overhead. Scan has proven to be a critical design function. Its area requirements are accepted and are no longer considered to be an overhead.
- As a result of implementing scan chains, scan adds only combinational logic to the existing edge-triggered flip-flops in the design.
- Scan does not require changes to the netlist for blocking X’s in the design. An unknown circuit response during test does not inhibit the application of the test itself.
- Scan has led to the development of several useful scan diagnostic solutions that rely on statistical analysis methods, such as counting the number of fails on the tester on various scan elements.
Adaptive Scan Architecture
Figure 2 shows the basic architecture of the Synopsys Adaptive Scan solution. This approach uses combinational elements that easily integrate with traditional scan solutions. The use of combinational circuitry in the scan-path ensures smooth implementation. Sequential elements for test compression are eliminated, which avoids problems with scan chain extraction, clocking, and integration with existing scan methodologies.
Figure 2: Synopsys Adaptive Scan Architecture
The combinational Adaptive Scan module placed at the front of scan chains enable adaptive alliances between the scan inputs and the scan chains. Using this methodology, one setting of the Adaptive Scan module can direct a scan chain to connect to a particular scan input. In another setting, the same scan chain can connect to a different scan input. When multiple scan chains connect to the same scan input, they receive the same scan data.
The Adaptive Scan architecture enables multiple dynamic settings within a given scan pattern, thus providing access to a large number of configurations for ATPG tests. Using this approach, the test pattern set enabling the maximum test coverage of the design can be applied. The output compressor allows for multiple internal scan chains of the design to be connected to fewer scan outputs. The output circuitry has redundant connections to allow for X-tolerance and ensures better diagnosis of the test data.
When this compression architecture is developed with a few combinational gates, a large number of shorter internal scan chains are accessible through a much smaller scan interface. This compression architecture has a direct positive impact on test data volume and test application time.
Integrated Adaptive Scan Flow
Smooth, seamless integration with existing, proven scan flows is an essential goal of test compression logic. Ideally, a user should reap the benefits of test compression without being aware of its existence. Figure 3 shows the implementation flow for Scan and Adaptive Scan for DFT Compiler MAX.
Figure 3: Scan and Adaptive Scan Implementation Flow
The Synopsys design-for-test synthesis solution integrates scan logic within the synthesis flow. This approach takes into account placement information and timing constraints. Scan insertion requires the user to specify design-for-test (DFT) constraints, including the number of scan chains required in the design. With integrated Design Rule Checking (DRC), the chains are architected and inserted to meet all clocking constraints and scan chain balancing requirements. Data associated with the inserted logic is seamlessly communicated to ATPG through automatically generated protocols. Adaptive Scan requires only two additional pieces of input from the user: the request for compression configuration, and the desired compression factor. The architecting and insertion steps do not require user input; typically, the interface between DFT and ATPG is created by the DFT process. The information to run ATPG with compression is automatically configured from the DFT generated protocol.
Physically Aware Test Compression
Test compression technologies relies on a larger number of shorter scan chain and can brings additional complexity and wiring congestion to physical design. With the number of scan chains increased by at least an order of magnitude, post DFT scan reordering is becoming inefficient. DFT compiler MAX integration in the Galaxy Platform delivers a physically aware test compression solution. Placement based scan chains partitioning allocates to the same chain, scan cells in immediate vicinity. It ensures minimal wiring and negligible impact on physical design compared to traditional scan design. The same intuitive Adaptive Scan flow described in Fig.3 can be used in Physical Compiler and automatically delivers a physically optimized test compression architecture with maximum ease of use.
Figure 4 shows the final layout of the scan chains for a sample design. This design implements 5 scan chains in traditional scan (above) and 30 internal scan chains for Adaptive Scan (below). The figures show similar placements of the scan cells for both designs. Adaptive Scan does not affect the routability of the final netlist.
Figure 4: Scan Chains for Traditional Scan and Adaptive Scan
Note that the technology provides near perfect compression efficiency in each design — near 12X compression (resulting in gains in test data volume and test application time) over traditional scan testing when the ratio of the number of internal chains to scan interface is limited to 12. In the examples, the compression technology provided an additional area overhead over scan of less than, or approximately, 10 gates per chain.
Next Generation Scan
Prior to the development of the Synopsys Adaptive Scan technology, designers and test engineers were forced to make fundamental tradeoffs in their test methodology. They had the difficult choice of minimizing either design flow impact or manufacturing test cost — the improvement of one had to come at the expense of the other.
With the introduction of DFT Compiler MAX, the tradeoff factor is eliminated. Powerful
Adaptive Scan technology can now be easily integrated into existing design flows while simultaneously reducing test cost.
By achieving significant test application time reduction with DFT Compiler MAX, designers can limit the cost of test for ICs without any negative impact to the overall die size. The reduction in test data volume and test application time can be used to increase the number of test patterns such that new defect mechanisms can be targeted for enhanced quality of test. With no significant change to the traditional scan solution, Adaptive Scan represents the next generation of scan technology.
About Rohit Kapur
Rohit Kapur is a Synopsys Scientist working in the area of Test Automation. Rohit is an IEEE Fellow and chairs the standards activities in the area of testing.
About Kirk Brisacher
Kirk Brisacher is Director of Corporation Applications Engineering for Test Automation at Synopsys. He has over 25 years of experience in IC design and management.testing.
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