Integrating Design and Process
More so than ever before, the link between design environment and process technology is critical to achieving design and manufacturing success at 90nm and below. Edward Wan (TSMC) and Paul Lai (Synopsys), describe the benefits of the recently announced collaboration on libraries and TSMC Reference Flow 6.0, resulting from the on-going technical partnership between TSMC and Synopsys.
The technical collaboration between Synopsys and TSMC has been sustained over a long period, with numerous successful technical programs completed over the past 6 years or so. This on-going collaboration has been critical to the success of both companies in developing a strong position in high-yield design and manufacturing solutions. The business aim from this technology partnership is lowered risk and improved time-to-volume for TSMC and Synopsys mutual customers.
The technical delivery is focused on linking together TSMC's advanced processes and libraries, and Synopsys' design platform to deliver the full benefits of TSMC's advanced technology features. Synopsys Professional Services also provides expertise in chip implementation and flow deployment services with Reference Flow 6.0.
Enhancing Library Access
This latest cooperation on methodology and technology builds on the core competencies of each organisation in providing silicon-validated TSMC libraries. TSMC’s standard cell and I/O libraries will now be available through Synopsys DesignWare Library, with Synopsys support.
This represents far more than a distribution agreement, since the deliverables include validation of TSMC’s libraries in TSMC processes through Synopsys’ Galaxy design platform. In addition, DesignWare Library arithmetic generators will be used to provide special cells with improved quality-of-results.
TSMC Reference Flow 6.0
This Reference Flow has been enhanced over several releases in order to address specific technology challenges with each new process generation.
Figure 1. Evolution of the TSMC Reference Flow
Release 6.0 emphasises specific measures to address power management and design for manufacture (DFM), and provides state-of-the art access to TSMC’s 90nm and 65nm process technology.
Low Power a Prominent Design Challenge
Within the dimensions of semiconductor optimization – performance, power, area and cost, power has become the primary issue for many designers. The drivers for low power optimization include battery life and packaging for mobile applications, and emerging technology issues with advanced geometries - such as leakage current, as well as the general rise in device complexity and higher clock frequencies.
TSMC has introduced innovations to both process and design technology in order to respond to the need for low power.
For example, TSMC’s first 65nm Nexsys technology is optimized primarily for low power. This is in direct response to customer feedback. Reference Flow 6.0 builds on the features integrated into Reference Flow 4.0 and 5.0 with support for advanced low-power design methodologies such as multi-voltage, leakage power optimization, deep sleep (shutdown) mode and static/dynamic voltage-drop analysis.
The use of multi-threshold CMOS (MTCMOS) as a complementary sleeper or footer cell in series with the standard cell element can eliminate the leakage path from the standard cell to ground. This technique can help reduce leakage current by more than 90 percent.
Synopsys offers a number of key features that enable power management within the Reference Flow 6.0. These include low power optimization, static and dynamic IR drop analysis and power network synthesis.
Synopsys' PrimeRail solution provides power network sign-off in the Reference Flow. PrimeRail is a full-chip dynamic voltage-drop and electromigration (EM) analysis solution that enables power network sign-off in Synopsys’ Galaxy™ Design Platform. PrimeRail extends Synopsys’ industry-leading sign-off solution to power networks. Building on Synopsys’ silicon-accurate Star-RCXT™, HSPICE®, NanoSim® and PrimeTime® sign-off technologies, PrimeRail delivers accurate modeling of memories and analog circuits.
Design for Manufacturing Determines Yield
With product lifecycles getting shorter, the time to achieve a fast volume ramp is more critical than ever. Unfortunately, continued scaling means process variance and pattern sensitivity has become severe, which has a major impact on yield.
Achieving fast volume ramp can only be achieved by enabling the information flow between design and manufacturing. TSMC has introduced specific measures to improve yield at 65nm, including:
- New 65nm design rules such as the Line End Rule and Zig-Zag Rule.
- New dummy metal fill utility, which provides better density uniformity and better insertion rate in the low density areas with multiple metal fill patterns.
- Half track wire spreading, which provides a more even distribution of wires, hence reducing coupling capacitance and critical areas.
Furthermore, TSMC has key initiatives in Design for Manufacturing (DFM) to drive TSMC process-specific capabilities into electronic design automation (EDA) tools from Synopsys to improve yield, performance, and ROI.
Design for Yield
One of the key aims from this collaboration is to ensure that manufacturing issues are considered at the beginning of the design phase and throughout the design cycle in order to achieve improved yield.
Reference Flow 6.0 incorporates a complete Synopsys-based RTL-to-GDSII solution utilizing the Galaxy Design Platform for RTL synthesis, physical implementation and sign-off, and the Discovery Verification Platform with VCS® and HSPICE® for RTL verification and circuit simulation.
As an integral part of the reference flow, extensive Galaxy support includes Design Compiler® logic synthesis solution, Power Compiler™ power management solution, DFT MAX 1-pass test synthesis solution, Jupiter-XT™ physical planning solution, Physical Compiler® and Astro physical implementation solutions, PrimeTime® and PrimeTime SI static timing and signal integrity sign-off solutions, PrimeRail power network sign-off solution, PrimePower full-chip power analysis solution, Star-RCXT™ parasitic extraction solution, Hercules™ PVS physical verification solution, and TetraMAX® automatic test generation (ATPG) solution. In addition, Synopsys Professional Services provides expertise in chip implementation and flow deployment services with Reference Flow 6.0.
Synopsys' Astro™ tool provides the physical design capabilities in the Reference Flow and supports TSMC's 90nm and 65nm recommended design guidelines. Astro — an integral part of Synopsys physical implementation solution and a key component of the Galaxy™ Design Platform — enables designers to place and route high-performance, complex and challenging designs while delivering excellent QoR with reduced design cycle time. Widely adopted today, Astro addresses physical effects like crosstalk, IR drop, electromigration, and antenna effects.
Using Astro, designers have successfully taped out numerous complex, high-performance and low-power designs at 130nm and below. With Astro in their flow, designers are realizing their yield and time-to-market requirements with significant performance and productivity gains. For the most advanced designs, Astro supports 90nm and 65nm design rules. Astro was used in the production tape out of the industry’s first 65nm design.
To ensure testability for TSMC's complex deep submicron processes, Reference Flow 6.0 includes Synopsys' DFT MAX comprehensive design for test (DFT) synthesis solution.
In addition to the Reference Flow 6.0, TSMC has also released two Design for Manufacturing (DFM) tool kits, Yield Plus and Yield Pro, which have been developed by TSMC in cooperation with its EDA partners, including Synopsys. These DFM kits use TSMC process-specific knowledge to improve yield upon a designer’s best effort, without increasing die size. Customers can contact TSMC for detailed information.
The continuing collaboration between Synopsys and TSMC is a proactive move towards ensuring that customer adoption of 65nm is both timely and successful.
By providing the Reference Flow, accessibility to TSMC’s technology is considerably enhanced as customers can be confident that the design flow and process technology combined offer a complete, low-risk solution from RTL to silicon.
Power is the primary concern for a growing number of design teams and the combined power closure solution from TSMC and Synopsys underpin the most advanced power management reference flow in the industry. Power management encompasses a new voltage scaling capability supporting multiple voltage islands, and a new power gating capability supporting fine grain MTCMOS to address current leakage.
Manufacturing and yield have become established as major design issues just as timing and signal integrity have been for some time. Global optimization of process technology, library, design automation, and design methodology can help to address the issues that create yield problems in 90- and 65nm processes. Such global optimization of tools and process technology can only be achieved through consistent and active, long-term flow collaboration, which has been the fulfilled aim of the Synopsys and TSMC partnership.
Edward Wan, Senior Director of Product Marketing, TSMC
Prior to joining TSMC NA, Edward Wan held many leadership roles in the industry, including CEO of Spike Technologies in Milpitas, VP of Worldwide Field Engineering at UMC in Sunnyvale, VP of Spectrum Services at Cadence in San Jose, and VP of Worldwide Customer Engineering Operations and North America Engineering at LSI Logic in Milpitas. Mr. Wan earned a B.S. in Electrical Engineering and Computer Science from the University of California, Berkeley.
Paul Lai, Group Manager Strategic Alliances, Synopsys
Paul is a veteran in the EDA industry with over 15 years experience. Prior to Synopsys,, he held various management positions in applications, marketing, and strategic programs at Gateway Design Automation, Cadence, and Viewlogic. Currently, he manages the Synopsys strategic alliance program with key foundries, such as TSMC. Paul earned B.S.E.E. and M.S.E.E degrees from Texas A&M University and an MBA degree from the University of California, Berkeley.
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