Successful SoC design for the diverse consumer market means that an array of technical and commercial challenges must be overcome. Ching-Hsiang Yang, Design Manager, at SUNPLUS Technology Co., Ltd outlines the stringent requirements for mixed-signal verification of the company’s designs, and the application of Synopsys’ Discovery AMS mixed-signal verification solution.
At SUNPLUS Technology Co., Ltd., we develop high quality, value-added integrated circuits (ICs) for the consumer market. Our microcontrollers, LCD ICs, multi-media devices and voice/music chips are at the heart of a range of products, including cell phones, laptops, PDAs, interactive toys and MP3 players. The demand for these products is endless, and consumers worldwide expect increased performance, more features and low prices for every new generation of products.
SUNPLUS’ design approach is based on the extensive re-use of core technology, such as multi-media audio/video engines, single-chip microcontrollers and DSP functions to enable the development of hundreds of products which are custom-designed to meet the exact needs of our customers.
The Design
SUNPLUS engineers depend on a quality verification flow to ensure the integrity of products, but when we recently developed a speech/music/sound processor circuit, we faced a new verification challenge. Our complex system-on-chip (SoC) contained a 16-bit CPU, as well as digital-to-analog and analog-to-digital converters, RAM, ROM and other elements. Each of these blocks required specific simulation techniques. In order for our engineering team to deliver a high-quality, low-cost product, we needed an efficient strategy to not only verify the individual digital and analog components that make up this complex, mixed-signal design, but also to verify the complete design in a full-chip context without compromising accuracy.
Although there are many solutions on the market that can verify sub-circuits, our team needed a solution that could verify individual mixed-signal components quickly and accurately, and more importantly, verify the entire chip’s functionality, timing and power. We also needed a solution that would be able to handle the large amounts of post-layout data and that could verify blocks written in both SPICE and Verilog that were highly interactive.
Limitations of Existing Verification Approaches
We have considered several verification strategies in an attempt to develop a solution that would meet our specific needs. One involved running a behavioral Verilog block-level simulation for timing and functionality, and then translating the results into large vector files as a test bench. We also considered modeling some components in a C-based language, at the transistor level for simulation. But both of these methodologies had serious drawbacks. First of all, the vector files from the Verilog block would be prohibitively large and would not be able to model any analog behavior in the blocks. Large files also meant long simulation run times, lengthening the entire verification cycle, which would adversely affect the time-to-market of our chip.
With the second approach, the C models would have to interact with the Verilog models, which would produce an unwieldy (and inaccurate) simulation flow. In addition, the team found that C-based models could not accurately mimic analog-type behavior such as RAM or ROM behavior.
Our challenge was to find a comprehensive verification flow which would generate highly-accurate simulation results, quickly. These two requirements are in constant opposition with each other and usually a design team must make a compromise on either accuracy or speed.
We performed a comprehensive evaluation of several commercial mixed-signal verification tools and selected Synopsys’ Discovery AMS as our solution of choice.
Fortunately, we found that Synopsys’ Discovery AMS could offer us the speed we need to quickly verify our entire design at the full-chip level without compromising on the accuracy of the results.
Discovery AMS Delivers
After evaluating and rejecting other solutions on the market, we chose Synopsys’ Discovery™ AMS. Discovery AMS is Synopsys’ mixed-signal verification platform based on three industry-leading golden simulators: VCS®, NanoSim™ and HSPICE®. These simulators are best-in-class stand-alone tools, and when combined through a new common interface, provide powerful simulation capabilities (Figure 1).
Figure 1: Discovery AMS is based on “golden” simulators HSPICE, NanoSim and VCS.
Discovery AMS enabled us to verify the analog and digital portions of the design with a combination of Verilog and SPICE. Using Verilog not only eliminated the need for any specialized C-based models, it also accurately modeled the RAM and ROM behavior that the C-based language could not.
The Verilog testbench streamlined the verification flow by eliminating the need for prohibitively large vector files. Discovery AMS also supported a combination of Verilog and Verilog-A models, which provides us with a seamless mixed-signal flow for functional and timing verification.
Figure 2: SUNPLUS design flow using Discovery AMS.
Discovery AMS provided full-chip, multi-level functional verification of our complex multi-media mixed-signal design with greater than 10x performance improvement over other solutions. We were able to achieve accurate simulation results on full-chip timing and power analysis. As a result of our success, we are now deploying Discovery AMS as our preferred solution in all of our production design flows.
Performance and Support
The excellent performance of the Discovery AMS solution meant that we were able to test three complete versions of the design with varying speeds and memory capacities prior to tapeout for first silicon.
We have received excellent support from Synopsys whenever there were questions regarding the Discovery AMS platform. With the success of the verification effort behind us, we plan to use Discovery AMS on a wide range of products that we produce for a very diverse and demanding consumer market. Fortunately, we found that Synopsys’ Discovery AMS could offer us the speed we need to quickly verify our entire design at the full-chip level without compromising on the accuracy of the results.
Ching-Hsiang Yang is currently Design Manager at SUNPLUS Technology Co., Ltd.
SUNPLUS is engaged in the research, development, design, testing and sales of high quality, high value-added consumer integrated circuits (ICs). We are dedicated to commercializing the communication and multimedia technology, helping people enjoy a more comfortable and convenient life.
In Sep. 1997, SUNPLUS became a listed company on Taiwan's Over The Counter stock exchange and was listed on the main board of the Taiwan Stock Exchange (TSE) in Jan. 2000. In Mar. 2001 SUNPLUS successfully launched its Global Depositary Receipts (GDRs) on the London Stock Exchange under the symbol "SUPD". It is the first Asian IC design company to issue GDRs. The company currently issued share capital is NT$ 77.75 billion.
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