High Accuracy Delay Calculation for Deep
Delay calculation for timing analysis must be both accurate and efficient. With deep-submicron processes, especially 90nm designs and below, it has become more of a challenge to calculate delays with appropriate accuracy. George Mekhtarian, product marketing manager on the Static Timing and Signal Integrity product teams at Synopsys, explains how Synopsys' Composite Current Source (CCS) delay calculation technology addresses the critical requirements for nanometer delay calculation.
Timing-driven cell-based design and optimization tools depend on efficient and accurate delay calculation in order to work. Timing delay is a function of the logic cell response and the associated interconnect. This requires that the drive capability of the logic cell is modeled, together with the timing characteristics of the receiver – that is, the capacitance of the load pins and the parasitic capacitances.
With 90nm processes, new physical effects mean that the old ways of modeling delays are no longer accurate enough. For example, input capacitances have become more complex, interconnect net impedance dominates cell delay, and voltage drop across the device can have a significant affect on delays. Because both transistor drive capability and input capacitance are becoming more complex and non-linear at 90nm and below, a new approach to delay calculation is required.
Existing Delay Models
The model most widely used today is the Non-Linear Delay Model (NLDM). NLDM uses lookup tables with load and slope as indexes. Because accuracy is proportional to the table size, one issue with this approach is that higher-accuracy calculations need larger tables. This can lead to memory blow-out. Also, with this approach voltage and temperature are linearly de-rated. Unfortunately, linear de-rating models do not hold up any more in DSM technologies. Vendors tend to overcome this by supplying multiple libraries – one for each operating condition. However, multiple databases invariably increase the cost of verifying and managing the design library.
Figure 1: Previous Driver Models Restricted by Limited Accuracy
Driver and receiver models are crucial to delay calculation. NLDM based driver models consist of a voltage source and a fixed drive resistance. Receivers are typically modeled using a fixed capacitor. Computing the response of a standard cell and the interconnect it drives using these models is challenging, particularly for highly resistive nets, such as top-level routes. In addition, delay and slew of signals are dependent on many variables. For example, voltage drop from non-ideal power networks can degrade performance significantly.
Integrated circuit designers are increasingly concerned with power issues. Lower Vdd values and multiple voltage regions (voltage islands) are used to reduce dynamic power. Libraries and electronic design automation (EDA) tools must support accurate delay calculation for these complex circuits seen in power-aware designs.
Power calculation itself requires very accurate information about timing, including switching windows and signal slew times. Advanced driver and receiver modeling are needed to generate this delay and slew data.
Similarly, signal integrity analysis is inter-dependent with static timing analysis and delay calculation. Accurate delay calculation is key to enabling significantly better quality of results for signal integrity analysis.
Composite Current Source Delay Calculation
Synopsys' Composite Current Source (CCS) delay calculation technology directly addresses all of the critical requirements for nanometer delay calculation. The CCS technology includes an advanced current-based driver model and a comprehensive receiver model to provide highly accurate delay calculation and signal integrity analysis.
Figure 2: CCS Provides Accurate Driver and Receiver Models
The driver model defines how the cell will source current to an arbitrary distributed resistor and capacitor network. CCS uses a time-varying, voltage-dependent non-linear current source to represent the drive capability of a cell. The receiver model represents the capacitance of a cell input pin. The CCS receiver model dynamically describes how the capacitance can vary due to factors including input slew and output load. It is a two-part representation, with dynamic adjustment of the capacitance during the transition.
This provides high accuracy for cells, including those with a very large Miller effect. The resulting measurements of slew and delay are typically within two percent of Hspice.
- Key advantages of CCS include:
- Accurate driver and receiver modeling of nanometer timing, including voltage and temperature variation.
- Easy characterization with HSpice current solutions.
- Extensible, scalable for statistical timing analysis and optimization.
The data representation for CCS has been incorporated into Synopsys' Liberty open library standard. Liberty is the most widely used library format in the electronics design automation (EDA) industry and is integral to the design flows of both semiconductor vendors and electronics designers.
Synopsys' widely used library format, Liberty, includes the .lib and .plib formats. Liberty is supported by more than 100 Semiconductor vendors with more than 750 submicron libraries, and by more than 30 EDA vendors supply over 75 production tools. It has evolved over 13 years along with technology and modeling needs and is a proven format, which can easily be extended to meet the needs of designers. Many EDA vendors already have Liberty translators in place.
Enhancements to Liberty include the addition of noise modeling capabilities, which will allow library suppliers and developers using this format to make their cell libraries ready for a comprehensive signal integrity flow for 90nm designs. Library Compiler can now compile libraries with noise modeling and write out a database. Synopsys tools can use this database like any normal library without any additional command.
Physical extensions (.plib) to Liberty allow vendors to include physical design data consistent with logical libraries to drive the new generation of EDA tools that comprehend both physical and logical information. These extensions to Liberty add key modeling capabilities for signal integrity. The library is then ready to be supported by a variety of EDA tools.
CCS builds on the comprehensive library modeling capabilities of Liberty. It supports high accuracy with a modest amount of additional data. Characterization for CCS is very straightforward. The library data is easily generated from HSpice measurements, leveraging the same transient simulations used in existing library characterization flows.
Customers are reporting that CCS provides clear advantages over other approaches: reduced design margins, high accuracy compared to circuit simulation, and low characterization overhead.
CCS is a foundation technology for Synopsys that is being deployed throughout the Synopsys Galaxy Design Platform to improve quality of results and to reduce turnaround time.
CCS today delivers accurate modeling and delay calculation to address sub-90nm static timing, signal integrity, and low power design challenges, and it is scalable for future requirements, such as statistical design.
George Mekhtarian is product marketing manager on the Static Timing and Signal Integrity product teams at Synopsys. He has 10 years of experience in electronic and EDA industry. Prior to Synopsys, Mr. Mekhtarian held various positions at Viewlogic and Teradyne's VLSI Test Equipment Division.
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