Compiler






Low Power USB 2.0 PHY IP for
   High Volume Consumer Applications

Gervais Fong, Product Marketing Manager with Synopsys, outlines the key benefits of a new low power USB 2.0 PHY IP core – the DesignWare® USB 2.0 nanoPHY, which provides built-in yield optimization to support implementation in advanced process technologies.

Overview
The USB protocol has become a pervasive standard in the world of computing and consumer electronics. While few design teams would today contemplate designing their own USB intellectual property (IP), this semiconductor IP is far from commodity silicon. Synopsys introduces a second USB 2.0 PHY IP product line (titled DesignWare® USB 2.0 nanoPHY), which has been further optimized for low power, area, manufacturing cost and system performance targeted to mobile and high volume consumer applications. This offers designers a choice of highly-differentiated USB PHY cores for 0.13-micron processes and below.

Introduction
With the proliferation of USB in mobile consumer devices, there are many key criteria that design teams look for when licensing IP, such as cost, system performance (interoperability), reliability, and power. Diligent technical evaluations have become a key part of the ‘make versus buy ’ decision or all but the simplest IP cores.

The competitive dynamics of global consumer electronics markets are driving down costs and putting further pressure on the design cycle. Consequently, overall design productivity and total cost of IP ownership are also issues that must be considered. For example, while the avoidance of design re-spins is a familiar design goal within most projects, the problem of reliability, in terms of field failures, can have a profound influence on the total cost of ownership. Manufacturing yield is another factor that can have a significant effect on lifetime cost. Both of these issues are directly affected by the key specification parameters of the USB PHY. Lastly, interoperability is another requirement that is critically important to interface IP. The issue of interoperability goes beyond just satisfying the requirements for ‘logo’ certification. Interoperability is a function of the design’s specification and operating margin, which in turn can impact device yield and the economics of manufacturing production.

With increasingly demanding specifications on power, driven by the need for longer operating life in portable devices, a low power design for the IP enables the overall SoC power budget to be maintained —a critical issue for battery-powered devices such as smart phones, MP3 players, digital cameras and flash drives. Within this context of an increasingly demanding set of business and technology drivers, Synopsys has introduced a second USB 2.0 PHY IP product line that is optimized for portable and high volume applications that require low power, small area, and high yield.

For the full white paper, download the pdf

Gervais Fong
Gervais Fong is a Senior Product Marketing Manager for Mixed-Signal PHY IP at Synopsys. Gervais has over 20 years of experience holding product marketing and product management positions covering ASIC, FPGA, EDA, and IP products. Gervais holds a Bachelor of Science degree in Electrical Engineering and Computer Science from the University of California, Berkeley

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©2007 Synopsys, Inc. Synopsys and the Synopsys logo are registered trademarks of Synopsys, Inc. All other company and product names mentioned herein may be trademarks or registered trademarks of their respective owners and should be treated as such.

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Gervais Fong
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 -DesignWare USB IP product line

"Despite USB being a ubiquitous standard, clearly not all USB PHY implementations are the same"