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DesignWare Verification IP Support for VMM
Neill Mullinger, Group Marketing Manager at Synopsys describes how verification IP support for the Verification Methodology Manual (VMM) reduces the time to first test for coverage-based verification.

Introduction
As ASIC and system-on-chip (SoC) designs continue to increase in size and complexity, there is an equal or greater increase in the size of the verification effort required to achieve functional coverage goals. This has created a trend in RTL verification techniques to employ constrained-random verification, which shifts the emphasis from hand-authored tests to utilization of compute resources. With the corresponding emergence of faster, more complex bus standards to handle the massive volume of data traffic there has also been a renewed significance for verification IP to speed the time taken to develop advanced testbench environments that include randomization of bus traffic.

Directed-Test Methodology
Building a directed verification environment with a comprehensive set of directed tests is extremely time-consuming and difficult. Since directed tests only cover conditions that have been anticipated by the verification team, they do a poor job of covering corner cases. This can lead to costly re-spins or, worse still, missed market windows.

Traditionally verification IP works in a directed-test environment by acting on specific testbench commands such as read, write or burst to generate transactions for whichever protocol is being tested. This directed traffic is used to verify that an interface behaves as expected in response to valid transactions and error conditions. The drawback is that, in this directed methodology, the task of writing the command code and checking the responses across the full breadth of a protocol is an overwhelming task. The verification team frequently runs out of time before a mandated tape-out date, leading to poorly tested interfaces. However, the bigger issue is that directed tests only test for predicted behavior and it is typically the unforeseen that trips up design teams and leads to extremely costly bugs found in silicon.

Constrained-Random Verification Methodology
The advent of constrained-random verification gives verification engineers an effective method to achieve coverage goals faster and also help find corner-case problems. It shifts the emphasis from writing an enormous number of directed tests to writing a smaller set of constrained-random scenarios that let the compute resources do the work. Coverage goals are achieved not by the sheer weight of manual labor required to hand-write directed tests but by the number of processors that can be utilized to run random seeds. This significantly reduces the time required to achieve the coverage goals.

Scoreboards are used to verify that data has successfully reached its destination, while monitors snoop the interfaces to provide coverage information. New or revised constraints focus verification on the uncovered parts of the design under test. As verification progresses, the simulation tool identifies the best seeds, which are then retained as regression tests to create a set of scenarios, constraints, and seeds that provide high coverage of the design.

How VMM Helps
The Verification Methodology Manual (VMM) for SystemVerilog, co-authored by Synopsys and ARM, defines a standard coverage-driven methodology for the creation of a constrained-random environment. This book describes in detail an object-oriented methodology for the creation of layered and reusable test environments that improve time to achieve coverage goals.

The Synopsys Reference Verification Methodology (RVM) is Synopsys’ implementation of the methodology recommended by the VMM for SystemVerilog. It includes a class library of VMM building blocks that enable faster development of the verification environment. In addition, the verification IP in the VCS® Verification Library provides scenario generators and transactors to significantly reduce testbench development time and effort. Design or verification engineers can easily create randomized scenarios at the upper levels of the environment that the VIP converts into the pin-level traffic at the interface. Figure 1 shows how the verification IP and RVM work together, while Figure 2 shows the resulting benefits for the project.

Figure 1
Figure 1: The combination of the VCS Verification Library and RVM

Figure 2
Figure 2: Constrained-random, coverage-driven verification with verification IP reduces schedule time and increases quality

Verification IP
Verification IP falls into two similar but distinct categories. Transactors model the behavior of a device on the bus or interface, and generate all of the transactions and sequences that can be used throughout the full breadth of the protocol. The traffic they generate can be used to stress the design under test and verify that it deals correctly with error conditions. Monitors are used to snoop the bus or interface to create a log of the transactions and to provide functional coverage information so that verification engineers can see which types of transactions have been verified. This protocol-based coverage information is included in the overall coverage results for the design under test.

Commercial Verification IP
One of the key values of commercial verification IP is that it significantly reduces testbench development time by providing proven off-the-shelf components that eliminate the need to write, test, and maintain many thousands of lines of code. Building verification IP is extremely challenging and time-consuming, requiring development of transactors, monitors, and scenario generators. For today’s complex standards such as PCI Express it can take more that 250,000 lines of code to model the protocol plus a similar number for the test environment. Commercial verification IP has become one of the key building blocks to accelerate testbench development by removing the need to develop all of this code in-house. Verification IP that supports coverage-based methodologies has a significant effect on overall verification productivity by allowing an automated approach to traffic generation.

DesignWare®
DesignWare Verification IP has been enhanced to support the layered VMM methodology, reducing the effort required to develop the testbench environment and resulting in a faster time to first test. It builds on the RVM class library and includes protocol-specific scenario generators that make it simple to develop tests to generate the desired random bus behavior.

With VMM and DesignWare Verification IP, protocol-based scenarios spread random seeds over the available simulators to rapidly achieve coverage of the possible transaction types and transaction sequences across the constrained random-conditions of the design. Tests are written at a high level by defining sequences and constraints, removing the need for developers to write individual read-write commands for every test. The scenario generator provided with the verification IP creates random objects within constraints defined by the verification engineer. The verification IP converts these into the relevant signal activity at the pin level to test the design interface.

A whitepaper, Five Vital Steps to a Robust Testbench with DesignWare Verification IP and Verification Methodology Manual (VMM) for SystemVerilog, describes how to rapidly create a constrained-random testbench. This whitepaper is available at: http://www.synopsys.com/cgi-bin/systemverilog/pdfr1.cgi?file=vip_in_rvm.pdf. A follow-up whitepaper, Advanced Techniques for Robust Testbench Development with DesignWare Verification IP and Verification Methodology Manual (VMM) for SystemVerilog, describes how to use such advanced techniques as callbacks and scenario generation in a constrained random testbench. This whitepaper is available at: http://www.synopsys.com/cgi-bin/systemverilog/pdfr1.cgi?file=dw_vip_and_rvm_wp.pdf

Summary
The VMM for SystemVerilog allows verification engineers to shift from a manual-labor effort to an automated approach to rapidly achieve functional and code coverage goals. With the VMM methodology, the testbench development is targeted towards the creation of an environment that can self-generate test sequences, rather than towards the creation of each individual scenario. There is never enough time given to verification engineers to completely verify the design. This approach leads to much higher coverage in the available time and finds problems not typically uncovered with directed tests.

DesignWare Verification IP speeds the time to first test by accelerating the development of the VMM-compliant environment. It not only saves time but also is designed to cover the full breadth of the bus or interface protocols, leading to more thorough verification.

About Neil Mullinger
Neill Mullinger is a Group Marketing Manager at Synopsys. In this role he focuses on verification IP and methodology support, including responsibility for Synopsys PCI Express Verification IP. Neill joined Synopsys in 2000 and has over 20 years experience in the hardware and EDA industries, bringing an extensive background of verification experience to product and methodology definition. Previous to Synopsys, Neill was employed at Mentor Graphics, where he held positions as an applications engineer and as a marketing manager.

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©2007 Synopsys, Inc. Synopsys and the Synopsys logo are registered trademarks of Synopsys, Inc. All other company and product names mentioned herein may be trademarks or registered trademarks of their respective owners and should be treated as such.

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 -VMM
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"DesignWare Verification IP has been enhanced to support the layered VMM methodology, reducing the effort required to develop the testbench environment and resulting in a faster time to first test."

"The VMM for SystemVerilog allows verification engineers to shift from a manual-labor effort to an automated approach to rapidly achieve functional and code coverage goals."