|
Return to
Synopsys Seminar Series
Registration is free
|
Verification Seminar Series
Seminar Overview
These seminars provide a forum for members of the electronic design community to learn about Synopsys’ latest technologies and methodologies. Intended for verification engineers and managers, these FREE technical seminars focus on the latest trends in system-to-silicon verification that will enable you to deliver the best products to your customers with predictable success.
Who Should Attend:
Verification engineers and managers who plan, execute or manage the SoC process and want to learn new techniques for improving productivity through the verification flow.
What You Will Learn:
Seminar topics include how to use Synopsys’ Discovery™ Verification Platform to efficiently adopt the latest functional verification methodologies while speeding closure, improving productivity and reducing risk.
Primary Seminar Agenda
| Time |
Topic |
Details |
| 8:30 a.m. |
Registration and Continental Breakfast |
|
| 9:30 a.m. |
Discovery Verification Platform Overview
|
The Synopsys Discovery Verification Platform provides a comprehensive solution for system-to-silicon verification. In this session, you will learn the latest from Synopsys on system level, functional and AMS verification, and how the complete Discovery platform can speed verification closure, improve productivity and reduce risk.
|
| 10:30 a.m. |
VCS Product Update
|
We will introduce the latest VCS technology updates, including SystemVerilog testbench automation, debug and analysis, verification planning, scripting, and more.
|
| Noon |
LUNCH |
|
| 1:00 p.m. |
VMM Applications Overview
|
VMM is the leading SystemVerilog-based methodology used worldwide to achieve predictable verification success. Our expert presenters will discuss details of several VMM applications that build on the VMM methodology, including the Register Abstraction Layer (RAL), Data Stream Scoreboard, and the new Performance Analyzer.
|
| 2:30 p.m. |
BREAK |
|
| 2:45 p.m. |
Low Power Verification
|
You will learn about the challenges of verifying low-power and multi-voltage designs. Additionally, our technical experts will introduce Synopsys’ low-power verification solutions for dynamic and static multi-voltage verification and present customer case studies.
|
| 4:15 p.m.
|
Conclusion and Prize Draw
|
|
|
Verification Seminar Schedule
| Date |
Location |
Registration |
| April 10, 2008 |
Irvine, CA |
CLOSED |
| May 12, 2008 |
Beijing, China |
Register by E-mail |
| May 14, 2008 |
Shanghai,China |
Register by E-mail |
| May 14, 2008 |
Lake Elmo, MN |
Register Now |
| May 16, 2008 |
Shenzhen, China |
Register by E-mail |
| May 20, 2008 |
Hsinchu, Taiwan |
Register by E-mail |
| June 12, 2008 |
Reading, UK* |
Register Now |
| June 17, 2008 |
Broomfield, CO |
Register Now |
| June 19, 2008 |
Boston, MA |
Register Now |
| July 8, 2008 |
Tokyo, Japan |
Coming Soon |
| July 11, 2008 |
Seoul, Korea |
Coming Soon |
| Sept. 3, 2008 |
Herzelia, Israel |
Coming Soon |
|
*Modified agenda
Registration is free
|
