Synopsys Eclypse Low Power Solution Seminar Series

Seminar Overview
Power has become an increasingly critical issue for the semiconductor industry, not only for traditionally power-conscious applications such as wireless, mobile, and consumer electronics, but also for high-performance applications that are now expected to meet energy conservation requirements while still achieving their performance goals. Shrinking process geometries have amplified the power issue, with leakage power becoming the source of as much as half of the total power consumption in a design. Furthermore, power densities become so concentrated in these smaller geometries that they cannot be properly supplied or dissipated.

Attend the FREE Synopsys Eclypse™ Low Power Solution Seminar to learn about Synopsys' end-to-end, silicon-proven advanced low power solution. Visionary perspectives on the challenges of low power, and how to address them, will be discussed by Synopsys and leading-edge low power companies. This seminar will also include a tutorial covering Synopsys' comprehensive, holistic approach to low power, where design and verification operate from a common, consistent basis for defining power intent.

Who Should Attend?
Project managers, design engineers, CAD managers, verification engineers and managers.

What You Will Learn

• UPF: Accellera's Unified Power Format (UPF 1.0) has become the industry standard for defining low power intent. This seminar will include an introduction to UPF, and will focus on the core set of constructs that are essential for the development of today's low power designs. Syntax for applying advanced low power techniques such as power gating, multi-voltage, and state retention will be covered.
• Low Power Design Techniques: Specific techniques that will be discussed are: voltage aware simulation and power state analysis, including Synopsys' unique power state transition validation; power state table (PST) implementation; power switch cell (MTCMOS) layout, analysis, and optimization; and power-optimized automatic test pattern generation (ATPG). The final steps will highlight equivalence checking of the final netlist to the golden RTL and UPF specification files, along with voltage-aware sign-off, with concurrent timing, signal integrity (SI), and power analysis.
• Low Power Methodology Manual: The flow and demos will follow the recommended methodologies outlined in the Low Power Methodology Manual (LPMM), co-authored by ARM and Synopsys.

Agenda*

Toronto and Ottawa Agenda

Schedule