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Synopsys Seminar Series
Registration is free
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Design Implementation Seminar Series
Seminar Overview
These seminars provide a forum for members of the electronic design community to learn about Synopsys’ latest technologies and methodologies. These FREE technical seminars are intended for IC design engineers and managers, and will be focused on the latest developments within Synopsys’ Galaxy™ Design Platform for IC implementation from RTL to silicon.
Who Should Attend:
IC design engineers and managers who want to learn new techniques to improve productivity and predictability.
What You Will Learn:
You will learn about new capabilities available with the most recent Galaxy tool releases and how to utilize them effectively to increase design implementation productivity and achieve performance, area and manufacturability goals. Seminar topics include RTL synthesis, design-for-test (DFT), design planning, place-and-route, timing, and signal integrity analysis and sign-off.
Primary Seminar Agenda
| Time |
Topic |
Details |
| 8:30 a.m. |
Registration and Continental Breakfast |
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| 9:30 a.m. |
Galaxy Design Platform Overview
Predictable Success for All Design Nodes |
The Galaxy Design Platform provides a complete RTL-to-GDSII implementation and sign-off solution for IC design. In this session, you will learn how the latest updates from Synopsys can help you achieve predictable design success through the use of integrated, proven flows and technologies.
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| 10:00 a.m. |
Design Compiler Update
The Most Advanced RTL Synthesis Solution |
Learn about the latest features and methodologies of the Design Compiler family, including low power, DFT, and equivalence checking. The technical presentation will cover improvements in DC Ultra QoR, runtime and usability, as well as an overview of topographical technology. In addition, new features in Formality and a recommended methodology for getting the best verifiable QoR will be discussed. Advanced topics will include low power test and small delay defect testing.
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| 11:30 a.m. |
LUNCH |
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| 12:30 p.m. |
IC Compiler Update
The Next Wave in Physical Implementation
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Learn about the latest IC Compiler updates, including integrated hierarchical design planning, advanced clock-tree synthesis, multi-voltage and MTCMOS design, concurrent multi-corner/multi-mode optimization, clock mesh, and physical datapath techniques.
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| 2:00 p.m. |
BREAK |
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| 2:15 p.m. |
PrimeTime Update
The Golden Rules for Sign-Off |
PrimeTime is the most trusted and advanced timing sign-off solution. Learn about the technology updates in the latest releases. Best practices for PrimeTime scripting will also be addressed.
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| 3:45 p.m.
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Hercules Update
Integrated Physical Verification
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Hercules provides the performance and capabilities needed for comprehensive verification with foundry-certified sign-off, including 45-nm readiness. This session will provide an update on the latest in physical verification technology.
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| 4:15 p.m.
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Star-RCXT Update
The Star for 45-nm Extraction
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Learn how Synopsys’ gold-standard Star-RCXT parasitic extraction solution addresses the process modeling requirements at 45-nm and beyond, and how its seamless integration with industry-leading implementation, physical verification, simulation and analysis tools enables superior design productivity.
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| 4:45 p.m.
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Conclusion and Prize Draw
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Design Implementation Seminar Schedule
| Date |
Location |
Registration |
| April 10, 2008 |
Irvine, CA |
CLOSED |
| May 12, 2008 |
Beijing, China |
Register by E-mail |
| May 14, 2008 |
Shanghai,China |
Register by E-mail |
| May 14, 2008 |
Lake Elmo, MN |
Register Now |
| May 16, 2008 |
Shenzhen, China |
Register by E-mail |
| May 20, 2008 |
Hsinchu, Taiwan |
Register by E-mail |
| June 17, 2008 |
Broomfield, CO |
Register Now |
| June 19, 2008 |
Boston, MA |
Register Now |
| July 8, 2008 |
Tokyo, Japan |
Coming Soon |
| July 11, 2008 |
Seoul, Korea |
Coming Soon |
| Sept. 3, 2008 |
Herzelia, Israel |
Coming Soon |
| Sept. 2008 |
Dresden, Germany |
Coming Soon |
| Sept. 2008 |
Munich, Germany |
Coming Soon |
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Registration is free
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