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Santa Clara, California
Technical Review of DAC Highlights
Overview
Didn't make it to DAC? Not to worry! Give us a day and we'll give you a condensed Synopsys MiniDAC.
If you are an IC design or verification engineer or manager who wants to learn new techniques to improve productivity and predictability, this is a can't-miss event!
This event provides a forum for members of the electronic design community to learn about Synopsys' latest technologies and methodologies. You will learn about new capabilities available with the most recent Galaxy™ Design Platform tool releases and how to utilize them effectively to increase design implementation productivity and achieve performance, area and manufacturability goals. Add to this Synopsys' Discovery™ Verification Platform and how to efficiently adopt the latest functional verification methodologies while speeding closure, improving productivity and reducing risk. You will also learn about the Synopsys Eclypse™ Low Power Solution, the industry's most comprehensive suite of proven tools, IP, methodologies and services that enable advanced low power design techniques.
Who Should Attend?
IC design and verification engineers and managers who want to take advantage of the latest technology advances and techniques to improve productivity and predictability.
Agenda
| Time |
Room 1 |
Room 2 |
| 8:30 a.m. |
Registration |
| 9:00 a.m. |
Eclypse: Power Intent, Architecture, and
Functional Verification |
Get to Market Early with SystemC™ TLM Virtual Platforms |
| 9:50 a.m. |
Eclypse: Implementation and Sign-off |
Advances in Circuit Simulation and
Mixed-signal Verification |
| 10:40 a.m. |
BREAK Visit partner displays in lobby |
| 11:10 a.m. |
Low Power Verification |
New Multi-core Enabled PrimeTime® and Practical Application of Statistical Analysis |
| Noon |
LUNCH Keynote speaker: Rich Goldman |
| 1:30 p.m |
SystemVerilog Verification Solution with VCS® |
Transistor-level Design Analysis and Sign-off using Star-RCXT™, HSIM™ and HSPICE® |
| 2:20 p.m |
Complete Physical Verification Solution Through 45nm |
Design Compiler® Graphical: Congestion Prediction and Removal During Synthesis |
| 3:10 p.m. |
BREAK Visit partner displays in lobby |
| 3:40 p.m. |
Advanced FPGA Implementation including DSP Modeling and Architectural Synthesis |
10M Gate Routing in Under ½ Hour with IC Compiler |
| 4:30 p.m. |
Confirma™ ASIC/ASSP Verification Platform |
Custom Design Preview |
| 5:20 p.m |
Conclusion/Raffles
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Schedule
| Date |
Time |
Location |
Registration |
| July 29, 2008 |
8:30 a.m. – 5:30 p.m. |
Santa Clara, CA |
CLOSED* |
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* On-site registration will be available the day of the event.
Venue Information
July 29, 2008 – Santa Clara, CA
8:30 a.m. – 6:00 p.m.
Hyatt Regency Santa Clara
5101 Great America Parkway,
Santa Clara, California, USA 95054
Tel: +1 408 200 1234
Map & Directions
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