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Synopsys at DAC 2008 -- Booth 1349
Synopsys AMS Verification Breakfast
AMS Verification and Moore’s Law… solutions for 45nm and beyond.
Tuesday, June 10, 2008
7:30am – 9:30am
Marriott Hotel, Ballroom E
The advancement of process technology to the 45nm node has enabled an ongoing increase of AMS content in SoCs for consumer, communications and computing applications. Robust functional verification requires higher productivity within both the analog and digital domains, along with comprehensive methodologies to accurately model mixed-signal behavior when "analog meets digital".
Come to this DAC breakfast meeting to hear a panel of industry experts discuss AMS verification challenges and their visions for solutions required at 45nm and beyond.
Who should attend
Analog designers, CAD engineers and digital verification engineers.
Panelists
Thomas J. Sheffler, PhD.
Sr. Principal Engineer
Rambus, Inc.
Jess Chen
Senior Staff Engineer
Qualcomm CDMA Technologies
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Henry Chang
Vice President
Designer's Guide Consulting, Inc.
Jeff McNeal
R&D Engineer
Synopsys IP Solutions Group
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Agenda
| 7:30-8:00 AM |
Complimentary breakfast |
| 8:00-8:10 AM |
Welcome and introduction of panelists; Paul Lo – Senior VP and GM for Synopsys AMS Business Group |
| 8:10-9:00 AM |
Panelist presentations |
| 9:00-9:15 AM |
Audience Q&A |
| 9:15AM |
Prize drawing |
| 9:20AM |
Conclusion |
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Register Now! for this free event at DAC! Seating is limited, so reserve your place today.
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