VERIFICATION IP

Accelerating Functional Closure: Synopsys Verification Solutions
This paper focuses on practical aspects of the verification process that can help reduce the time taken to reach functional closure. It is based on experiences of working directly with many leading edge semiconductor companies implementing modern verification technologies and methodologies. It will discuss the power of constrained random simulation using an object-oriented testbench and verification IP to provide better control and reuse. It will then show how this leads to more effective use of available resources such as simulation compute farms and engineers’ time. Since coverage is a measure of how effectively the design is being verified, this paper will address when and how to implement code and functional coverage and use it to achieve functional closure.

Five Vital Steps to a Robust Testbench with DesignWare Verification IP and Verification Methodology Manual (VMM) for SystemVerilog
Design teams are turning to advanced and unified verification methodologies that leverage multiple technologies to handle the biggest verification challenges. Constrained random verification leverages compute resources and functional coverage technology to provide more testing with less test code development. Setting up a constrained random test environment, however, can seem like a difficult task, especially when you consider that environments need to be flexible, scalable, and reusable. The infrastructure for constrained random verification requires more planning and structure, but the benefits in the end are well worth the investment. This paper shows how to start performing constrained random verification quickly and easily with DesignWare VIP and VMM for SystemVerilog.

Advanced Techniques for Building Robust Testbenches with DesignWare® Verification IP and Verification Methodology Manual (VMM) for SystemVerilog

This paper is the second in a series. It discusses the benefit of using constrained random verification and briefly recaps the Five Vital Steps to a Robust Testbench with DesignWare Verification IP and Verification Methodology Manual (VMM) for SystemVerilog paper. The primary focus of the discussion is on using advanced techniques with DesignWare VIP and VMM for SV to build a robust constrained random testbench. The techniques that will be discussed are:

• Constraints
• Factories
• Callbacks
• Coverage
• Scenario generation

Advanced Stimulus Generation with DesignWare Verification IP and Verification Methodology Manual for SystemVerilog
This paper shows how to perform advanced stimulus generation using DesignWare Verification IP and VMM for SystemVerilog. It focuses on two key topics - Exceptions and Scenario Generation. Exceptions represent protocol deviations or injected errors. Although errors are to be avoided in design, creating non-compliant conditions is an important part of the verification effort. In addition, it is fairly easy to generate a stream of discrete transactions each one unrelated to the others to verify the design but often protocol traffic really occurs as sequences. The ability to create scenarios which are sequences of protocol activity is the key to effectively testing and verifying the design. This paper goes into the details of successfully creating exceptions and generating scenarios.