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MIXED-SIGNAL IP
The Good? The Bad? The Ugly? IP Perspectives from Vendor to SoC Integrator
While the IP landscape will always look different when seen through the eyes of SoC designers, integrators and IP vendors, these players gain a significant advantage if they see each others’ roles more clearly. This paper explores the perspectives of three such players and their approach to working with mixed-signal IP. After taking in each perspective, life with IP might be a little easier for everyone.
Life Begins at 65 – Unless You Are Mixed-Signal?
The old school of analog designers, exemplified by pioneer Bob Pease, is becoming an extinct species. But the demand for analog/mixed-signal IP blocks has never been greater, especially at 65 nm and below. Can this demand be met by using externally designed 3rd party analog/mixed-signal IP? Or, is the implementation of revolutionary changes to traditional work flows and analog design processes a suitable option? Which solutions that help in increasing design efficiency are currently on the table? In the future, which side of the table will analog designers of Bob Pease’s generation sit: the IP provider or the chip company? Or, are their skills redundant for the 65 nm analog challenges?
Implementing Physical Layer Connectivity IP in Deep Sub-Micron Technologies
The physical layer is responsible for the transmission of the raw bit stream over the PHYsical transport medium and is the lowest layer within the OSI network model. With high-speed interfaces such as the serial protocols USB 2.0, PCI Express®, SATA, and DDR2, the PHY provides the bridge between the digital and modulated parts of the interface. The trend is to integrate these mixed-signal interfaces into SoC’s that are manufactured in digital logic deep sub-micron technologies with channel lengths of 65-nm and 45-nm. These technologies are tuned for digital integration and pose challenges to the mixed-signal circuit designer:
- Low operating voltages reduce head room for analog circuits
- Circuit design techniques need to combat increased leakage
- Circuit designer awareness of STI, HCI, NBTI, and proximity effects that impact long term performance and reliability
After an introduction to circuit and process trends in deep sub-micron technologies, this article will present a complete protocol solution using the high speed memory DDR2 interface as an example. This is followed by a description of the implementation challenges of integrating IP into an SoC. The article concludes with a proposal for production testing a high-speed serial PHY’s.
High Performance Connectivity IP: Avoiding Pitfalls When Selecting an IP Vendor
The demand for connectivity IP for high-speed serial busses such as USB 2.0, PCI Express®, SATA, DDR2 and HDMI is increasing as standard interfaces in applications such as single chip recordable DVD CODEC’s and MP3 players. In order to stretch battery life of these chips, the semiconductor technologies require ultra-low power derivatives of high-performance logic manufacturing processes, enabling production of very low-power chips for these mobile platforms and small-form factor devices. Today many of these chips are manufactured in 90 nm, and the ramp for 65 nm design starts has been more aggressive than expected. In this paper, we will discuss how to select a third party IP vendor, how to verify third party IP, and some of the gotcha’s when integrating third party IP, with a special focus on the SerDes-based PHYs for PCI Express and SATA as well as PHYs for USB and DDR2.
Beyond DDR2 400: Physical Implementation Challenges in Your SoC Design
DDR2 SDRAM is an increasingly common memory solution for designs requiring improved data bandwidth capabilities and enhanced signaling features. However, the benefits of DDR2 SDRAM are coupled with significant physical implementation challenges at data rates above 400 Mbps. This paper discusses how using complete, integrated DDR2 SDRAM memory physical interface IP solutions can significantly reduce the risks, such as interoperability, associated with combining discrete memory subsystem blocks. Packaged as a complete, integrated place-and-route hard macro, or as scalable sub-macros, third-party DDR2 SDRAM PHY IP can deliver predictable 800 Mbps system performance and significantly reduce development time.
Low Power USB 2.0 PHY IP for High-Volume Consumer Applications
The USB protocol has become a pervasive standard in the world of computing and consumer electronics. While few design teams would today contemplate designing their own USB intellectual property (IP), this semiconductor IP is far from commodity silicon. Synopsys introduces a second USB 2.0 PHY IP product line (titled DesignWare® USB 2.0 nanoPHY), which has been further optimized for low power, area, manufacturing cost and system performance targeted to mobile and high volume consumer applications. This offers designers a choice of highly-differentiated USB PHY cores for 0.13-micron processes and below.
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