GENERAL IP

Building a Total Quality Experience into Silicon IP:
Delivering DesignWare® Silicon IP into SoC Designs
Now more than ever, developers of complicated SoC design rely on silicon IP (SIP) both internally developed and from third parties to achieve their time-to-market goals. Too often, SIP providers have oversold the capabilities of their products. It’s time for a new supplier-buyer relationship. After nearly 10 years of practice, SIP vendors must deliver a “Total Quality Experience” to buyers. But judging the quality of SIP is more than just answering yes to rows of questions in a matrix. Quality is measured most effectively through direct customer feedback and systematic quality investigation. SIP providers must now step up and deliver a new experience for their SoC customers.

Reverse Disaggregation—How Silicon IP Will Change the Semiconductor Supply Chain
The title might seem like marketing jargon. But often, if you create an interesting expression, the words help conjure up a picture of what is actually taking place. The frame of this picture is IP or SIP. IP providers will play a central role in the next big landscape change in the semiconductor supplier market, reversing a trend that began over forty years ago—the disaggregation of the supplier market in semiconductors. Reverse disaggregation will drive the creation of a new supply chain for the development of a new generation of products, full featured and assembled at zero cost. IP will influence how the new supply chain is created, reversing the disaggregation that has marked the industry until now.

IP TOOLS

Reducing AMBA-based SoC Design Time by More Than 50% Using coreAssembler™
To meet increasing time to market pressures, designers have been using more IP to reduce the amount of new code that needs to be created for the design. Additionally on-chip bus standards such as AMBA® have been widely adopted, providing designers with a standard that allows them to integrate multiple complex IP blocks as a subsystem into an SoC. This article describes how using a knowledge-based IP design and verification flow with coreAssembler can greatly reduce the time needed to assemble, configure, verify and implement a configurable AMBA subsystem with IP architected and packaged for use and intelligent assembly and configuration. The focus of this article will be on the assembly of the subsystem with synthesis, verification and packaging of the subsystem summarized.