DESIGNWARE LIBRARIES

Implementing Floating-Point IP for the Right Accuracy and Quality of Results (QoR)
With a rich library of DesignWare Floating-Point IP, chip designers have many implementation choices that can significantly affect the final quality of results. These choices are especially important when using synthesizable IP (such as the IP in the Synopsys DesignWare® Library), where good implementation choices can optimize the tradeoffs between area/delay and accuracy. While the IP can provide extremely high levels of accuracy, pushing accuracy higher than the application requires simply compromises area and/or performance. This whitepaper describes several types of flexible tradeoffs available to designers, including the benefits of specifying complex floating-point operations rather than multiple separate operations.

Enabling Rapid Adoption of the AMBA 3 AXI Protocol-based Design with
Synopsys DesignWare IP
To successfully develop an AMBA™ 3 AXI™ protocol-based design in the shortest time requires a comprehensive set of synthesizable IP, verification IP and an automated method to assemble the entire SoC subsystem. The AMBA 3 Advanced eXtensible Interface (AXI) protocol builds on the benefits of the AMBA 2.0 standard offering greater performance and flexibility. But with this flexibility comes complexity. This paper shows how the DesignWare® IP solution for the AMBA 3 AXI protocol enables designers to quickly and easily integrate high speed designs based on the AMBA 3 AXI protocol.

Designing Using the AMBA 3 AXI Protocol
The need for higher performance applications is driving the requirement for a new age of on-chip communication infrastructure. Increasing the clock frequency no longer addresses this higher performance requirement, as the bottleneck is inherent in the existing bus infrastructure. This paper examines the advantages of the new AMBA® 3 Advanced eXtensible Interface (AXI™) protocol for on-chip bus infrastructure, and how it revolutionizes the future of high-performance system-on-chip (SoC) interconnect. It describes the AMBA 3 AXI protocol feature set that makes it suitable for the new high-performance, low-latency and low-power designs. It also examines the verification tools and intellectual property (IP) necessary to successfully complete design and verification in today’s reduced development design cycle.

Coding Guidelines for Datapath Synthesis

This document summarizes two classes of RTL coding guidelines for the synthesis of datapaths:

• Guidelines that help achieve functional correctness and intended behavior of arithmetic expressions in RTL code.
• Guidelines that help datapath synthesis to achieve best possible QoR (Quality of Results).