|The Linley Group: Synopsys ARC HS Processors: High-Speed Licensable CPU Cores for Embedded Applications|
This white paper describes the Synopsys DesignWare® ARC® HS (High Speed) processor family. ARC HS34 and HS36 are the first members of the company’s newest family of licensable CPU cores for embedded applications that need 32-bit RISC performance in a small silicon footprint with minimal power consumption. The Linley Group prepared this report after evaluating ARC HS performance data and technical features.
Tom R. Halfhill, Senior Analyst, The Linley Group; J. Scott Gardner, Senior Analyst, The Linley Group
|Reducing Power Consumption in Mobile Applications with High-Speed Gear3 MIPI M-PHY-IP |
This white paper discusses how a MIPI M-PHY using High-Speed Gear3 operation can provide power-efficient high-speed links for a variety of mobile chip-to-chip communication standards and protocols, such as JEDEC Universal Flash Storage (UFS), USB 3.0 SuperSpeed Inter-chip (SSIC), and PCI-SIG M-PCIe®, each of which are optimized for its particular purpose. The paper then explains how designers can solve signal integrity challenges in implementation, including channel loss, interconnect, and electromagnetic interference (EMI) issues.
Sérgio Silva, Project Director, MIPI M-PHY IP, Synopsys, Inc. ; Hezi Saar, Product Marketing Manager, MIPI IP, Synopsys, Inc.
|How HDMI 2.0 Will Enrich the Multimedia Experience|
With an install base of over 3 billion devices worldwide1, HDMI has become the de facto multimedia interface for all digital home and mobile multimedia devices. To offer consumers the ultimate home theater experience, SoC designers must understand the new features offered by HDMI 2.0, as well as additional features that will drive the adoption of HDMI in industrial, office, and gaming applications.
This white paper describes the HDMI 2.0 specification and compares the new revision of the HDMI specification with the previous versions, HDMI 1.3 and HDMI 1.4. It explains how HDMI 2.0 will almost double the bandwidth from 10.2 Gbps to 18 Gbps to offer 4K video formats at 60 Hz frame rate for an ultra-high definition (ultra-HD) experience on digital TVs. It discusses additional features, such as CEC 2.0, 21:9 frame formats, multi-view video, and HDCP 2.2 for digital rights management. Finally, it will explain HDMI 2.0’s impact on new markets and applications.
Manmeet Walia, Product Marketing Manager, Synopsys Inc.; Luis Laranjeira, R&D Manager, Synopsys Inc.
|Achieve 10X DRAM Bandwidth Improvement with a DDR Controller Read Reorder Buffer|
The read reorder buffer (RRB) is a silicon-proven architectural enhancement available in DesignWare uMCTL and uMCTL2 DDR memory controller IP products. This white paper will explain the concept of the read reorder buffer and explain how a read reorder buffer can improve memory bandwidth. It then concludes with experimental results showing how DRAM controllers with different architectures can achieve vastly different DRAM bus utilizations of 10%, 66%, or 100% from the same input traffic stream, depending on whether the architecture has no RRB, an RRB with external scheduling, or an RRB with content-addressable memory (CAM)-based scheduling.
Marc Greenberg, Product Marketing Director, DDR Controllers, Synopsys
|Scaling ADC Architectures for Mobile & Multimedia SoCs at 28-nm & Beyond|
This white paper compares the attributes of common ADC architectures, including the Successive Approximation Register (SAR)-based architecture, for use in medium- and high-speed 28-nm ADCs. It describes advantages of the SAR-based architecture that reduce power consumption and area usage for mobile and multimedia SoCs. Finally, it presents the DesignWare SAR-based ADC family for 28-nm and explains how it benefits from advanced process nodes through adherence to the area and power scaling paradigms of digital circuitry.
Carlos Azeredo-Leme, Analog Design, Senior Staff, Synopsys, Inc.; Pedro Figueiredo, Analog Design, Staff, Synopsys, Inc.; Manuel Mota, Technical Marketing Manager, Synopsys, Inc.
|The Rise of SIP Subsystems: What is the Value to Silicon Architects and SoC Designers|
The semiconductor IP (SIP) market arose when SIP vendors created IP functions that mirrored those found in the discrete semiconductor market and made those functions available to SoC designers in the form of hard or soft SIP blocks. As the SoC and SIP markets evolved, it was a natural evolution that many discrete SIP functions be converged into larger blocks that mimic system-level functions (i.e. subsystems). This whitepaper discusses how the use IP subsystems to reduce the level of effort designers must expend to create highly complex SoC designs will represent the future of the SoC development in the semiconductor industry.
Rich Wawrzyniak, Sr. Market Analyst: ASIC & SoC, Semico Research Corp