DesignWare IP White Papers 

Optimizing LPDDR4 Performance and Power with Multi-Channel Architectures
LPDDR4 offers huge bandwidth in a physically small PCB area and volume; up to 25.6 GByte/s of bandwidth at a 3,200 Mbps data rate from a single 15mmx15mm LPDDR4 package when two dies are packaged together. LPDDR4 builds on the success of LPDDR2 and LPDDR3 by adding new features and introducing a major architectural change. This white paper explains how LPDDR4 is different from all previous JEDEC DRAM specifications.
Marc Greenberg, Director of Product Marketing for DDR IP, Synopsys

Addressing Three Critical Challenges of USB Type-C Implementation
As designers create new products and system-on-chips (SoCs) with USB Type-C support, they need to be aware of partitioning challenges. The SoC and system design must be partitioned to support the specification’s requirements for precision analog circuitry plus high voltage/high current switches, and Type-C management software must be partitioned to execute on the processor, internal microcontroller, microcontroller in a power management IC, and/or on an external dedicated USB Type-C chip. This white paper describes key challenges and suggests solutions for designers of USB Type-C products and SoCs with native USB Type-C support.
Morten Christiansen, Technical Marketing Manager, USB, Synopsys

Designing an Efficient DSP Solution: Choosing the Right Processor and Software Development Toolchain
Read about key challenges in DSP implementation from both hardware and software application perspectives, and learn how a properly selected and configured DSP processor coupled with an advanced software development toolchain can overcome these challenges. This white paper describes how to generate tight, efficient, and maintainable DSP code for a platform consisting of an IP core based on a specialized instruction-set architecture (ISA) coupled with a DSP-aware toolchain.
Abhishek Bit, CAE, Synopsys; Jamie Campbell, CAE, Synopsys; Sergey Yakushkin, R&D Engineer, Synopsys

Delivering High Quality Analog Video Signals with Optimized Video DACs
In most modern consumer equipment, multimedia content is processed in the digital domain. However, analog video transmission requires the digital video content conversion to the analog domain. To accomplish this, a video digital-to-analog (DAC) must be used. This paper outlines the most common analog video signal standard-specifications that multimedia SoCs must support. It describes the key characteristics and features of a DAC solution optimized for video applications. The paper addresses system-level techniques that together with an optimized video DAC will enable SoC designers to deliver power-efficient and feature-rich multimedia devices.
Antonio Leal, Analog Design Manager, Synopsys

True Random Number Generators for Truly Secure Systems
Random numbers form the basis, or root, of most security systems. Yet the methods for generating random numbers vary widely in practice as well as efficacy. Over time, many popular randomization algorithms and circuit implementations have been shown to be provably flawed. The paper will examine current methods for generating random numbers based on various sources of entropy as well as their associated attack techniques, including physical, statistical, and electronic methods.
David A. Jones, Senior FAE, Synopsys

Safety in SoCs: Accelerating the Road to ISO 26262 Certification With Processor IP
Today’s system-on-chip (SoC) designs are becoming more complex, increasing the pressure on verification and design teams to deliver fully functional designs. Recent studies have shown that over 50% of the development time on a complex IC is now being spent on verification, revealing the severity of the problem project teams are facing. As more SoC designs are used in electronic systems deployed in safety-critical applications, adhering to functional safety standards such as ISO 26262 has become an important consideration when defining the verification methodology. This white paper outlines the key requirements for ISO 26262 certification and demonstrates how to accelerate the development of safety-critical IP and SoCs through the use of out-of-the-box safety-ready IP with advanced verification qualification tools and methodologies.
Steven Parkinson, R&D Engineer, Synopsys

 

 


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