DesignWare IP Videos
|Featured USB Video: Industry's First Certified 10G USB 3.1 IP Solution Demonstrated at IDF16|
Join Gervais Fong and Mick Posner as they demonstrate industry's first certified USB 3.1 Gen2 IP solution. Shown at Intel Developer Forum 2016, the video also displays the high performance designers can expect from DesignWare USB 3.1 IP in their SoCs.
Gervais Fong, Senior Product Marketing Manager, Synopsys; Mick Posner, Director Product Marketing Director, Synopsys
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|Featured PCIe Video: DesignWare IP for PCI Express 4.0 Lane Margining|
This demonstration shows the lane margining feature of the DesignWare IP for PCI Express 4.0 as defined in the latest specification, allowing system designers to assess performance variation tolerance for design robustness.
Rita Horner, Senior Technical Marketing Manager, Mixed Signal IP, Synopsys
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|Featured IP Prototyping Kit Video: Using Juno ARM Development Platform for USB 3.0 IP Software Development|
See how to use the Juno ARM® Development Platform with Synopsys DesignWare® USB 3.0 IP Prototyping Kits to start implementing IP in your ARM-based SoCs in minutes. The video describes how the kits are connected via the new Juno HapsTrak3 Adaptor as well as a logical link reference design that enables communication between AXI and the ARM Thin Link.
Hugo Neto, Technical Marketing Manager, IP Prototyping Kits, Synopsys
||Designing 7-nm IP, Bring It On Moore!|
In keeping with Moore’s Law, discover how Synopsys is developing 10nm/7nm IP for SoC designs. Learn how tradeoffs are made in electrostatics, leakage, pattern, manufacturability and transistor performance to meet PPA requirements. See how quantum effects impact FinFET designs in terms of fin width, fin height and anything that impacts bandgap. Technology can be scaled to 7nm, bringing performance and power improvements.
Navraj Nandra, Sr. Director of Marketing, Synopsys
|Featured Bluetooth Video: A Complete Bluetooth® IP Solution Developed by Synopsys and Mindtree|
This demonstration shows how you can enable wireless connectivity for energy-efficient IoT SoCs with Synopsys’ DesignWare Bluetooth® PHY IP on 55-nm process and Mindtree’s software stack and link layer IP. Each IP is qualified by the Bluetooth Special Interest Group and compliant with the latest specification.
Manuel Mota, Technical Marketing Manager, Synopsys
|What is ASIP Designer?|
See how Synopsys’ ASIP Designer tool suite uses a single input specification to generate an SDK featuring a highly optimizing C compiler, instruction-set simulator, assembler, linker and debugger, and synthesizable RTL. The tool’s rapid architectural exploration capability and the ability to make rapid changes in your processor model make it easy to optimize the processor for your specific requirements.
Bo Wu, Technical Marketing Manager and Steve Cox, Sr. Manager, Business Development, Synopsys
|IoT Always-on Demonstration using the DesignWare® Smart Data Fusion IP Subsystem|
This demonstration shows always-on functions including 9D sensor fusion and voice activation, gesture recognition and face detection to control MP3 playback. The demo platform includes a silicon-based MCU with an integrated ARC® EM5D-based Smart Data Fusion Subsystem and 2 megabytes of MONOS embedded flash.
Rich Collins, Product Marketing Manager, DesignWare Sensor IP Subsystem, Synopsys
|Synopsys Accelerates IoT Designs with Comprehensive IP Portfolio|
John Blyler, editorial director for IoT Embedded Systems talks to Ron Lowman about how Synopsys has re-architected and optimized its comprehensive IP portfolio to address connectivity, security, energy-efficiency and sensor processing requirements of IoT designs.
John Blyler, Editorial Director, IoT Embedded SystemsRon Lowman, Strategic Marketing Manager for IoT, Synopsys
Learn more about DesignWare IP for IoT solutions
|Synopsys ARC EM DSP Processors for Low-Power Embedded Systems|
Learn about Synopsys' DesignWare® ARC® EM DSP Family, consisting of the ARC EM5D, EM7D, EM9D, and EM11D processors that are specifically designed for ultra-low power embedded DSP applications. The processors are ideally suited for DSP-intensive functions such as sensor fusion, voice detection, speech recognition and audio processing that are common in Internet of Things (IoT) and other embedded applications.
Angela Raucher, Product Line Manager, ARC EM Processors, Synopsys
|Featured MIPI Video: Accelerate UFS Host IP Prototyping & Integration with DesignWare IP Prototyping|
Reduce UFS Host IP prototyping and integration effort using DesignWare IP Prototyping Kits. The kits provide the essential hardware and software elements needed to start implementing the IP in an SoC in minutes. The included simulation testbench, reference drivers, and application examples enable designers to start their own IP software development right out of the box.
Hugo Neto, Technical Marketing Manager for IP Prototyping Kits, Synopsys
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|Object Detection Demo with DesignWare EV Family of Vision Processors|
In this speed sign detection demo, see how the DesignWare EV vision processors offer high accuracy and performance for embedded vision applications. The EV vision processors are built on a multicore architecture that is optimized for vision applications, and implement a convolutional neural network (CNN) that can operate at more than 1000 GOPS/Watt.
Speaker: Mike Thompson, Sr. Product Marketing Manager, ARC & Embedded Vision Processors, Synopsys
|Energy Harvesting, Sensors & SoCs for the IoT Era|
Today’s IoT devices require components such as sensors and implanted medical devices to be autonomous and have life-long renewable sources of energy. This session describes the IoT market trends, SoC components required for the IoT such as sensors and implantable devices, and energy harvesting methods.
Jamil Kawa, Scientist, Synopsys
|embARC Open Software Platform Accelerates Development of ARC Processor-based Embedded Systems|
Learn about Synopsys’ embARC Open Software Platform, an easily accessible and productive solution for developing ARC processor-based embedded software. It gives software developers online access to a comprehensive suite of free and open-source software that eases the development of code for IoT and other embedded applications. Device drivers, operating systems and middleware ported to and optimized for ARC processors are available for download free of cost from the embARC.org website.
Allen Watson, Product Marketing Manager, Synopsys
|Featured NVM Video: Introducing DesignWare® Medium Density NVM IP|
Learn about Synopsys’ new DesignWare Medium Density Non-Volatile Memory (NVM) IP, an alternative to embedded flash memory without additional masks or processing steps for Analog ICs, reducing die cost by up to 25%.
Angela Raucher, NMV Product Line Manager, Synopsys and Soheil Modirzadeh, Marketing Programs Manager, Synopsys
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|Featured IP Subsystems Video: 9D Sensor Fusion Demonstration Featuring DesignWare Sensor IP Subsystem|
See Synopsys’ 9D sensor fusion demo that calculates motion orientation using three independent 3-axis sensors. The 9D sensor fusion hardware and software demo platform is based on Synopsys' DesignWare ARC EM Starter Kit and consists of the ARC EM processor, filtering and math accelerators, and interfaces such as UART, SPI, I2C and GPIO.
Rich Collins, Product Marketing Manager, Synopsys
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|Physical IP Development on FinFET - There's Nothing Planar About It! (12:30-2:00)|
This video discusses the FinFET characteristics of physical IP design and how they differ from planar devices. It will describe the impact FinFETs have on existing circuit designs and layout topologies for widely used IP such as DDR, USB, PCI Express, embedded memories and logic libraries.
Navraj Nandra, Sr. Director of Marketing for the DesignWare Analog/Mixed Signal IP, Embedded Memories and Logic Libraries, Synopsys
|Featured HDMI Video: Synopsys Demonstrates DesignWare HDMI 2.0 IP Solution|
Join us in the Synopsys HDMI lab to see a demo of our HDMI 2.0 transmitter and receiver performance and features such as 4K video, YCbCr 4:2:0 colorimetry, and the HDCP 2.2 content protection standard.
Luis Laranjeira, R&D Manager, Synopsys
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|Synopsys Launches DesignWare ARC Software Development Platforms|
Learn how Synopsys’ new DesignWare® ARC® Software Development Platforms help designers accelerate software development for their ARC processor-based designs. These ready-to-use, integrated hardware and software platforms provide software developers an out-of-the-box solution that incorporates the hardware and software needed to significantly accelerate the code development, including silicon-proven ARC processors, peripheral I/O, operating systems and drivers, all on a single, integrated platform.
Allen Watson, Product Marketing Manager, ARC Tools, Synopsys
|Featured Ethernet Video: Reducing EMI in SerDes PHYs using Spread Spectrum Clocking|
Learn what spread spectrum clocking (SSC) is and why it is important to high-speed SerDes design.
John Stonick, Synopsys Fellow, Solutions Group, Synopsys and Rita Horner, Sr. Technical Marketing Manager, Mixed Signal IP, Synopsys
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|Synopsys’ New DesignWare ARC HS Processors for Next-Generation Embedded Systems|
Learn about Synopsys’ new DesignWare® ARC® HS processors, a new family of 32-bit high-speed, low-power processors optimized for power efficiency (DMIPS/mW) and area efficiency (DMIPS/mm²).
Mike Thompson, Sr. Product Marketing Manager, ARC Processors, Synopsys
|Designing IP for FinFET Technology: The Opportunities and Challenges|
FinFETs are emerging as the device technology of choice at advanced nodes. This introduces new design challenges for IP development, which require knowledge of and experience in designing with FinFETs to ensure design success. This video describes the benefits and challenges of transitioning from planar to FinFET technologies and how IP plays a significant role in this transition.
Jamil Kawa, R&D Director, Synopsys
|Featured DDR Video: Synopsys Discusses its New DDR4 Memory Interface IP|
Sean O'Kane from ChipEstimate.com interviews Navraj Nandra about the Synopsys' DesignWare DDR4 IP product release. They discuss DDR4 SDRAM, its market, and their predictions for DRAM.
Navraj Nandra, Synopsys and Sean OKane, ChipEstimate.com
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|Featured SATA Video: SATA Host IP Demo Using a Port Multiplier and FIS-Based Switching|
See how DesignWare SATA host controller IP issues read/write commands to Port Multiplier-attached drives, while FIS-based switching interleaves the data packets to enhance the utilization of the 6 Gbps SATA link bandwidth
Mat Loikkanen, SATA R&D, Synopsys
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|Featured Analog Video: Synopsys Demonstrates Next Generation DesignWare Data Converter IP solution|
Synopsys shows the next generation DesignWare ADC IP 12-bit 250 MSPS, delivering outstanding performance, robustness and ultra low power dissipation of up to 50% less than previous generations.
Manuel Mota, Technical Marketing Manager, Synopsys and José Carmo, Application Engineer, Synopsys
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|Introducing the DesignWare HPC Design Kit|
Learn how Synopsys' DesignWare HPC Design Kit, a single package containing high-speed and high-density memory instances and standard cell libraries, allow designers to optimize all their on-chip CPU, GPU and DSP IP cores for maximum speed, smallest area or lowest power. Hear about the results achieved on the Imagination PowerVR™ Series6 GPU core.
View more DesignWare Embedded Memories, Logic Libraries and Embedded Test Videos>