DesignWare IP Videos 

View the industry's first demonstration of USB 3.0 SSIC successfully completing compliance testing while running with a MIPI® M-PHY. Synopsys' DesignWare® USB 3.0 SSIC Host and Device Controllers offer low gate counts and low power consumption, and support standard PHY interfaces. The low-power DesignWare multi-gear MIPI M-PHY, with support for HS-Gear3, is interoperable with a variety of protocols to reduce designers' risk of adopting new interfaces.
Eric Huang, Product Marketing for USB Digital IP, Synopsys and Hezi Saar, Product Marketing for MIPI IP, Synopsys

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Understand what adaptive equalization is and how it relates to CTLE or DFE equalization in a PHY.
Rita Horner Sr. Technical Marketing Manager, Mixed Signal IP, Synopsys, and David Rennie, Sr. Analog Design Engineer, Mixed Signal IP, Synopsys

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With the months required to design, fabricate, and test high-speed PHYs, how can designers have confidence in their designs before they see the silicon results?
Rita Horner Sr. Technical Marketing Manager, Mixed Signal IP, Synopsys, and David Rennie, Sr. ANalog Design Engineer, Mixed Signal IP, Synopsys

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This demonstration highlights the DesignWare UFS Host and MIPI UniPro IP solutions’ proven system-level interoperability, which lowers integration risk for mobile SoCs.
Lokesh Kabra, R&D Manager for MIPI Controllers

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Sean O'Kane from ChipEstimate.com interviews Navraj Nandra about the Synopsys' DesignWare DDR4 IP product release. They discuss DDR4 SDRAM, its market, and their predictions for DRAM.
Navraj Nandra, Synopsys and Sean OKane, ChipEstimate.com

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See how Fast Switching technology reduces HDMI switching time from 5 seconds to 1 second. Using a BluRay player and a multimedia player, this video demonstrates the DesignWare HDMI Receiver IP solution's high-performance interoperability.
Antonio Costa, R&D Manager for the DesignWare HDMI Controller IP solutions, Synopsys

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See how DesignWare SATA host controller IP issues read/write commands to Port Multiplier-attached drives, while FIS-based switching interleaves the data packets to enhance the utilization of the 6 Gbps SATA link bandwidth
Mat Loikkanen, SATA R&D, Synopsys

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Synopsys shows the next generation DesignWare ADC IP 12-bit 250 MSPS, delivering outstanding performance, robustness and ultra low power dissipation of up to 50% less than previous generations.
Manuel Mota, Technical Marketing Manager, Synopsys and José Carmo, Application Engineer, Synopsys

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This demonstration will feature the post-silicon interactive automation capabilities of the DesignWare STAR Silicon Browser, which utilizes the DesignWare STAR Memory System's embedded test & repair IP solution.
Yervant Zorian, Chief Architect, Synopsys, Gevorg Torjyan, R&D Engineer, Synopsys

Learn how the pre-integrated, configurable DesignWare® SoundWave Audio Subsystem helps you achieve great audio with a complete, SoC-ready subsystem solution. Also, join us in the Synopsys Sound Room, where we test our high-definition audio solutions, to see the SoundWave Audio Subsystem in action using a HAPS® FPGA-Based Prototyping System.
Henk Hamoen, Sr. Product Marketing Manager, Synopsys