See how Fast Switching technology reduces HDMI switching time from 5 seconds to 1 second. Using a BluRay player and a multimedia player, this video demonstrates the DesignWare HDMI Receiver IP solution's high-performance interoperability.
Antonio Costa, R&D Manager for the DesignWare HDMI Controller IP solutions, Synopsys

Synopsys shows the next generation DesignWare ADC IP 12-bit 250 MSPS, delivering outstanding performance, robustness and ultra low power dissipation of up to 50% less than previous generations.
Manuel Mota, Technical Marketing Manager, Synopsys and José Carmo, Application Engineer, Synopsys

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DisplayLink shows Synopsys USB 3.0 Device, PHY, and HDMI IP in Mass Production chips in real products.
Eric Huang, Product Manager, Synopsys and Theo Goguely, Product Manager, DisplayLink

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Learn how the pre-integrated, configurable DesignWare® SoundWave Audio Subsystem helps you achieve great audio with a complete, SoC-ready subsystem solution. Also, join us in the Synopsys Sound Room, where we test our high-definition audio solutions, to see the SoundWave Audio Subsystem in action using a HAPS® FPGA-Based Prototyping System.
Henk Hamoen, Sr. Product Marketing Manager, Synopsys

Synopsys demonstrates the DesignWare SATA 6 Gb/s AHCI Host controller and PHY implemented on Synopsys' HAPS FPGA-Based Prototyping Solution interoperating with a commercially available SATA 6 Gb/s device.
Scott Knowlton, SATA Product Marketing Manager and Mat Loikkanen, SATA R&D, Synopsys

Utilizing the LeCroy's protocol analyzer, exerciser and test suite, Synopsys demonstrates PCI Express 3.0 transactions through the DesignWare PCI Express 3.0 IP implemented on the Synopsys HAPS FPGA prototyping system.
Scott Knowlton, PCIe Product Marketing Manager, Torrey Lewis, PCIe R&D, Synopsys

This demonstration will feature the post-silicon interactive automation capabilities of the DesignWare STAR Silicon Browser, which utilizes the DesignWare STAR Memory System's embedded test & repair IP solution.
Yervant Zorian, Chief Architect, Synopsys, Gevorg Torjyan, R&D Engineer, Synopsys

Synopsys demonstrates proven system-level interoperability utilizing Synopsys' DesignWare MIPI CSI-2 and DSI host controller as well as the DesignWare MIPI D-PHY IP solution
Hezi Saar, Product Marketing Manager, DesignWare MIPI IP; Miguel Falcao Sousa, R&D Manager, Solutions Group

This video demonstrates the fully characterized, silicon-proven capabilities of the DesignWare MIPI M-PHY IP solution, highlighting its silicon performance as well as its electrical characteristics, which exceed target specifications.
Celio Albuquerque, R&D Manager, DesignWare MIPI PHY IP

This video provides a high level view of popular MIPI protocols and helps you get up to speed with latest mobile market innovations. We will also introduce IP solutions that can help you differentiate your products in the mobile market space.
Hezi Saar, Product Marketing Manager, DesignWare MIPI IP

With the release of the IEEE 802.1 specifications for Audio Video Bridging (AVB) designers can now include this functionality in their designs with the DesignWare® Ethernet QOS core. This demonstration will show how a Ethernet design can easily be configured to support AVB capable networks.
John Swanson, Senior Manager, Synopsys

This demonstration features LeCroy’s Summit T3-16 Protocol Analyzer, Summit Z3-16 Protocol Exerciser and the Summit Z3-16 Test Platform to test a PCI Express 3.0-based design for compliance to the PCI Express 3.0 specification. The design-under-test (DUT) utilizes the DesignWare® IP for PCI Express 3.0.
Featuring: John Wiedemeier, Product Manager, LeCroy; Scott Knowlton, Product Marketing Manager, Synopsys

Utilizing a DUT that implements the DesignWare IP for PCI Express 3.0, this demonstration features Agilent’s complete test solution for PCI Express 3.0 and the Digital Test Console to check for compliance to the PCI Express 3.0 specification.
Featuring: Yenyi Fu, Product Manager, Agilent; Scott Knowlton, Product Marketing Manager, Synopsys

By using DDR Hard PHY IP, you achieve: quicker integration, easier timing closure, better performance and less silicon area. With a hard PHY, all the IP is supplied by one IP vendor and includes I/Os. Hard PHYs have lower jitter, better duty cycle, an overall superior clock strategy and use identical circuits for every bit of the parallel DDR interface reducing skew. In addition, hard PHYs implemented in test chips are equivalent to the customer's PHY where as soft PHYs are different GDSII every time.
Synopsys Super Stars

Live from DesignCon 2010, see how the DesignWare DDR3/2 IP enables automatic timing compensation for voltage and temperature changes, per bit deskew adjustments in the datapath, and on-chip capabilities for measuring write and read data eyes.
Graham Allan, Product Marketing Manager, Memory Interface IP; Vishal Thareja, Test Engineer

Synopsys shows how fixed video and audio patterns are transmitted by the DesignWare HDMI TX controller and PHY. See the image quality improve as resolution of video test pattern is increased from 480p to 720p to 1080p, 60 Hz frame formats. Also see the EDID info collected by TX Controller/PHY Display Data Channel (DDC) from the sink device (DTV) to support negotiation and find the best supported color format and frame rate.
Manmeet Walia, Product Manager for Mixed-Signal PHY IP, Synopsys

See a live demonstration of the 45-nm DesignWare PHY and controller IP for PCI Express® 2.0 operating in a single-lane configuration at 5 GT/s. The demonstration verifies 5 GT/s operation using the PCI® Tree software and executes Reads and Writes between the demo hardware and a PC to show throughput performance levels.
Scott Knowlton, Sr. Produt Marketing Manager, Synopsys

See how Synopsys demonstrates proven interoperability with the complete DesignWare® SATA IP solution, consisting of digital controllers, mixed-signal PHY and Verification IP. This video consists of hardware demonstrations for the DesignWare SATA AHCI Host, Device, PHY and 6 Gb/s IP solutions.
Mat Loikkanen Sr. R&D Engineer, Synopsys; Mick Posner Sr. Product Marketing Manager, Synopsys

See how Global Unichip (GUC) utilized Synopsys' silicon-proven DesignWare® SATA IP in its Solid State Device (SSD) GP5080 platform to demonstrate a netbook boot-up time of less than half a minute. The hardware platform consists of a high-performance 32-bit ARM7 processor, SATA 3Gb/s interface, SLC/MLC NAND Flash management of up to 4 channels, 8 banks with ECC.
Kurt Huang, Director of Marketing, Global Unichip Corp.

See firsthand the test equipment and custom boards developed and used by Synopsys to verify our DDR IP. Witness full speed write and read data eyes, at speed functionality testing, duty cycle and phase error tests and jitter analysis results.
Graham Allan, Product Marketing Manager, DDR IP

Join Synopsys in our lab to see how we deliver a compliant, robust PCI Express 2.0 PHY and enable visibility into the link performance through unique on-chip diagnostics.
Navraj Nandra, Marketing Director MSIP