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Synopsys DesignWare IP for PCI Express 3.0 Passes First PCI-SIG PCIe 3.0 Compliance Workshop
Achronix Tapes Out Industry's First FinFET-based System-on-Chip Using Synopsys' IC Compiler and IC Validator
Synopsys Announces Earnings Release Date for Second Quarter Fiscal Year 2013
HiSilicon Technologies Tapes Out 50+ Million Instance ARM Processor-based SoC Using Synopsys IC Compiler

^MAY 21	Discovery-AMS for Mixed-Signal Verification Webinar
^MAY 22	Transaction Debug with Verdi3 Webinar
^MAY 23	DFTMAX Compression, Hierarchical Test and iJTAG Webinar
^MAY 28	Samsung and Synopsys share their perspective on 14-nm FinFET design Webinar
^MAY 29	Verilog-to-Verilog Equivalence Checking Using ESP Webinar
^MAY 30	Custom Layout Using the Laker Custom IC Solution Webinar
^JUN 03	PrimeTime SIG Dinner: Technology Panel - Advanced ECO Methodology Austin, TX
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Conquering HSPA+ Modem Design

3 Easy Ways to Accelerate Development of your Embedded SoC

Achieving Predictable and Highly Reliable 10G Backplane Designs

Late-Stage Leakage Recovery using the Lynx Design System

Case Study: Design and FPGA-Prototyping of an Application Specific Processor for Embedded Vision

Ease Debug and Control of Network Software Using Virtual Prototypes to Do Full System Simulation

FinFET White Paper
TSMC and Synopsys on FinFET Technology

New! Galaxy Custom Router
Analog and special net routing for custom and digital IC design

Virtual Prototyping White Paper
Virtual Prototypes: When Where and How to Use Them

Processor Designer White Paper
Design of Embedded Vision Processors

Equivalence Checking White Paper
A Safe Approach to Hierarchical UPF Verification in Formality

VIP Fact Sheet
Ten Things You Should Know About Verification IP

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