The following TSMC Nexsys Memory Compilers for TCBN90LP and TCBN65LP are available from Synopsys:
| Description | Feature | Available |
|---|
| Single Port SRAM With Redundancy - HD - Standard-vt and High-vt mixed logic / High-vt SRAM | 1K~256Kbits; 0.999μm2 bitcell | Today |
| Single Port SRAM Without Redundancy - HD - Standard-vt and High-vt mixed logic / High-vt SRAM | 32~256Kbits; 0.999μm2 bitcell | Today |
| 2 Port Register File with Redundancy - Standard-vt logic / High-vt SRAM | 64~256Kbits | Today |
| 2 Port Register File without Redundancy - Standard-vt logic / High-vt SRAM | 1K~256Kbits | Today |
| 2 Port Register File without Redundancy - High-vt logic / High-vt SRAM | 1K~256Kbits | Today |
| Dual Port SRAM without Redundancy - Standard-vt logic / High-vt SRAM | 64~256Kbits | Today |
| Dual Port SRAM without Redundancy - High-vt logic / High-vt SRAM | 64~256Kbits | Today |
| ROM | 1K~2Mbits | Today |
| ROM - HVT | 1K~2Mbit | Today |
| Description | Feature | Available |
|---|
| Single Port SRAM With Redundancy - Mixed-vt logic, High-vt SRAM | 1K~256K | Today |
| Single Port SRAM Without Redundancy - Mixed-vt logic / High-vt SRAM | 128~288K | Today |
| Dual Port SRAM - Standard-vt logic / High-vt bit cell | 32~1152K | Today |
| 1 Port Register File - Standard-vt logic / Standard-vt SRAM bit cell | 32~18K | Today |
| 2 Port Register File - Standard-vt logic / High-vt bit cell | 16~72K | Today |
| ROM - Standard-vt logic / Standard-vt SROM | 64~1179K | Today |
| 1 Port Register File - High-vt logic / High-vt SRAM bit cell | 32~18K | Today |
| 2 Port Register File - Mixed-vt logic / High-vt bit cell | 16~72K | Today |
| Single Port SRAM Without Redundancy - High-vt logic / High-vt SRAM | 128~288K | Today |
| Dual Port SRAM - Mixed-vt logic / High-vt bit cell | 32~1152K | Today |
| ROM - High-vt logic / High-vt SROM | 64~1152K | Today |
For more information on the TSMC Nexsys Memory Compilers for TCBN90LP and TCBN65LP Contact Us
The increasing popularity of portable consumer applications such as next generation hand held games, feature rich cell phones and personal media players continues to drive the need for low power designs. To address this need, Synopsys is distributing TSMC's complete family of low power memory compilers which are specifically targeted for these types of applications.
Developed by TSMC for the CLN90LP and CLN65LP processes, the TSMC Nexsys™ Memory Compilers are further validated by Synopsys to ensure smooth integration with the Synopsys Galaxy™ and Discovery™ Platforms.
In addition, the Nexsys Memory Compilers are fully compliant to the TSMC-9000 Quality Assurance process.
The high standard of quality assurance, validation through the Synopsys Galaxy and Discovery platforms combined with the fully silicon validated status of the compilers ensure ease of use and predictable results.
TSMC and Synopsys have been committed to providing SoC designers with the best tools, flows and IP for the last decade.
Design teams can leverage a predictable path from RTL to GDSII through the validated integration of the TSMC Libraries and Memory Compilers with the Synopsys Galaxy and Discovery platforms with TSMC's Reference Flow 6.0.
Complementing the TSMC Nexsys Memory Compilers for TSMC 90LP and 65LP are the proven TSMC Nexsys Standard Cells and I/Os, which are currently available to all DesignWare Library licensees.
