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DesignWare ARC xISS

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The Synopsys DesignWare® ARC® xISS product is a high-performance, instruction-accurate simulator for the DesignWare ARC 600 and ARC 700 processor family. It supports the full ARCompact ISA including xMAC, multiply and XY memory DSP options. The models are fully re-entrant so that multiple instances may be used in the same design to simulate a multi-core system.

xISS offers simulation performance of 20+ MIPS which makes it a good solution for early software development and debug before hardware is available. It works seamlessly with GDB and the MetaWare® Debugger. The debugger invokes a xISS simulation as a target, and the xISS simulation operates within the debugger just as other hardware or software targets do, providing a stable and productive development platform.

xISS comes with an optional TLM2.0 SystemC™ wrapper that offers TLM2.0 sockets for memory accesses as well as interrupts. The resulting Loosely-Timed (LT) SystemC models use blocking transactions to ensure interoperability with third party models. There as well is support for temporal decoupling using a quantum keeper.
 

Accelerate Time-to-Market
  • Never wait for boards - Engage your software team early in the development process
  • Quickly iterate through multiple system configurations to determine the best options for your requirements
  • Increase the number of develop/debug/optimize cycles to ensure your product meets your requirements
Increase Developer Productivity
  • Less waiting - Fast simulation for software development and tuning
  • Integrated with software debuggers, including GDB and the MetaWare Debugger
  • Configured with processor choices made in the DesignWare ARChitect™ Processor Configurator