Virtual Prototyping
Accelerate pre-RTL embedded software development, hardware/software integration, and system validation
Architecture Design
Quickly explore tradeoffs in your SoC architecture to achieve optimal product performance and cost to avoid over- or under-design
FPGA-Based Prototyping
Accelerate the creation of your ASIC prototype with a high-speed hardware prototyping environment including a comprehensive software flow
Core Optimization
Differentiate your product with the right combination of performance, power and area for your most design-critical cores
Design Flow Deployment
Optimize your design flow to address the latest design challenges
Physical Design Assistance
Leverage our tape-out proven flows and project experience to implement your very-deep submicron chip
IP Integration & SoC Verification
Get to market faster and reduce SoC design and verification cost by applying best practices in RTL creation and functional verification
Synopsys' DesignWare® ARC® xCAM product works with the DesignWare ARChitect™ Processor Configurator to automatically provide 100% cycle-accurate models that reflect system-on-chip (SoC) designers specific hardware configurations of DesignWare ARC IP. These models allow design verification and provide detailed performance analysis of software before finalizing the hardware design. An underlying generator engine automatically creates the DesignWare ARC xCAM Cycle Accurate Model by translating the original Verilog RTL into 100% cycle accurate C++ or SystemC models. With the DesignWare ARC xCAM solution, multiple models are generated to compare alternative approaches against specific code early in the design process, assisting in choosing an optimal configuration.
The DesignWare ARC xCAM product installs within the DesignWare ARChitect IP Configurator to generate cycle-accurate models. Once installed, the modeling component can be added to the processor design within DesignWare ARChitect and options set. The DesignWare ARChitect solution then builds a 100% cycle-accurate model in minutes.
Upon completion of the DesignWare ARC IP configuration, the DesignWare ARChitect solution uses the DesignWare ARC xCAM product to add a step into the build process, generating a cycle-accurate model that reflects the user's configuration automatically.
The DesignWare ARC xCAM model operates as a target within GDB and the MetaWare® Debugger. Using the DesignWare ARC xCAM solution's 100% cycle-accurate models are as simple as using an ISS, a DesignWare ARCangel™ prototyping system or actual hardware.
At any time during the run, access the following profiling information:
Forward cycle counts
Backward cycle counts
Mispredicts
Instruction counts
View profiling data:
Per function - to determine function with the most cycle counts
Per line of source or disassembly - to find candidates for custom instructions within a function
Per count - ordered from highest to lowest counts across the entire application
