Synopsys' DesignWare® MIPI® M-PHY IP is compliant to the latest MIPI Alliance M-PHY specification and supports a wide range of high-speed interfaces for mobile applications including JEDEC Universal Flash Storage (UFS), USB SuperSpeed InterChip (SSIC), PCI-SIG M-PCIe™, MIPI UniPro, DigRF v4, Low Latency Interface (LLI) and future CSI-3 and DSI-2.
The DesignWare MIPI M-PHY IP supports High-Speed Gear1, Gear2 and Gear3 rates A/B along with Type-I and Type-II low-speed capabilities. The M-PHY’s modular architecture allows implementation of a variety of transmitter and receiver lanes to meet a broad range of applications and all modes outlined in the protocol specification. A sophisticated clock recovery mechanism and power efficient clock circuitry are designed to guarantee the integrity of the clocks and signals required to meet strict timing requirements. The DesignWare MIPI M-PHY supports large and small amplitudes, slew rate control and dithering functionality for optimized electromagnetic interference (EMI) performance.
DesignWare MIPI Complete Solution Datasheet DesignWare MIPI M-PHY Datasheet