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DesignWare MIPI M-PHY IP Solution

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Synopsys' DesignWare® MIPI® M-PHY IP is compliant to the latest MIPI Alliance M-PHY specification and supports a wide range of high-speed interfaces for mobile applications including JEDEC Universal Flash Storage (UFS), MIPI Low Latency Interface (LLI), USB SuperSpeed InterChip (SSIC), PCI-SIG M-PCIe™, MIPI DigRF v4, UniPro, and future CSI-3 and DSI-2.

The DesignWare MIPI M-PHY IP supports High-Speed Gear1, Gear2 and Gear3 rates A/B along with Type-I and Type-II low-speed capabilities. The M-PHY’s modular architecture allows implementation of a variety of transmitter and receiver lanes to meet a broad range of applications and all modes outlined in the protocol specification. A sophisticated clock recovery mechanism and power efficient clock circuitry are designed to guarantee the integrity of the clocks and signals required to meet strict timing requirements. The DesignWare MIPI M-PHY supports large and small amplitudes, slew rate control and dithering functionality for optimized electromagnetic interference (EMI) performance.

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DesignWare MIPI M-PHY Datasheet
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  • Compliant to MIPI M-PHY specification v3.0
  • Interoperable with multiple protocols, enabling a future-proof design
  • High-Speed Gear1, Gear2 and Gear3 A/B modes
  • Support M-PHY Type-I and Type-II M-PORTs
  • Low-speed PWM Gears in Type-I LS implementation
  • Common lane configuration support for mobile IC applications
  • Fast entering and recovery from/to low power modes
  • Optimized EMI performance through the use of slew rate control and dithering
  • Large and small amplitude
  • Sophisticated clock recovery mechanism
  • Power efficient clock circuitry for high-speed and low-speed clock generation
  • Advanced test features simplifies debug and production procedures
  • Available in advanced process nodes
MIPI MPHY 1Tx2RX - TSMC 40LP 2.5VSTARsSubscribe
Multi-Gear MIPI M-PHY Supporting SSIC, LLI, Unipro, UFS, CSI-3 and DSI-2 protocolsSTARsSubscribe
Multi-Gear MIPI M-PHY Supporting DigRFv4 protocolSTARsSubscribe

  Description MIPI MPHY 1Tx2RX - TSMC 40LP 2.5V
  Name dwc_mipi_mphy_1tx_2rx-tsmc_40lp25
  Version 1.13a
  STARs Open and/or Closed STARs
  myDesignWare Subscribe for Notifications
  Product Type DesignWare Cores
  Documentation
  Download dwc_mipi_mphy_1tx_2rx-tsmc_40lp25
  Product Code 4718-0
  
  Description Multi-Gear MIPI M-PHY Supporting DigRFv4 protocol
  Name dwc_multi-gear_mipi_mphy_type2
  STARs Open and/or Closed STARs
  myDesignWare Subscribe for Notifications
  Product Type DesignWare Cores
  Documentation
  
  Description Multi-Gear MIPI M-PHY Supporting SSIC, LLI, Unipro, UFS, CSI-3 and DSI-2 protocols
  Name dwc_multi-gear_mipi_mphy_type1
  STARs Open and/or Closed STARs
  myDesignWare Subscribe for Notifications
  Product Type DesignWare Cores
  Documentation
  Product Code 9930-0