Virtual Prototyping
Accelerate pre-RTL embedded software development, hardware/software integration, and system validation
Architecture Design
Quickly explore tradeoffs in your SoC architecture to achieve optimal product performance and cost to avoid over- or under-design
FPGA-Based Prototyping
Accelerate the creation of your ASIC prototype with a high-speed hardware prototyping environment including a comprehensive software flow
Core Optimization
Differentiate your product with the right combination of performance, power and area for your most design-critical cores
Design Flow Deployment
Optimize your design flow to address the latest design challenges
Physical Design Assistance
Leverage our tape-out proven flows and project experience to implement your very-deep submicron chip
IP Integration & SoC Verification
Get to market faster and reduce SoC design and verification cost by applying best practices in RTL creation and functional verification
Synopsys' DesignWare® USB 1.1 PHY is a complete mixed-signal PHY IP solution, designed for single-chip, USB 1.1 integration in both device and host applications. The USB 1.1 PHY includes all the required logical, geometric and physical design files to implement USB 1.1 capability into a SoC design and fabricate the design in the designated foundry. The USB 1.1 PHY is capable of transmitting and receiving serial data at both full-speed (12 Mbps) and low speed (1.5 Mbps) data transfer rates. The USB 1.1 PHY is available today in 90 nm, 130 nm and 180 nm CMOS digital logic process technologies.DesignWare USB 1.1 PHY Datasheet
