Virtual Prototyping
Accelerate pre-RTL embedded software development, hardware/software integration, and system validation
Architecture Design
Quickly explore tradeoffs in your SoC architecture to achieve optimal product performance and cost to avoid over- or under-design
FPGA-Based Prototyping
Accelerate the creation of your ASIC prototype with a high-speed hardware prototyping environment including a comprehensive software flow
Core Optimization
Differentiate your product with the right combination of performance, power and area for your most design-critical cores
Design Flow Deployment
Optimize your design flow to address the latest design challenges
Physical Design Assistance
Leverage our tape-out proven flows and project experience to implement your very-deep submicron chip
IP Integration & SoC Verification
Get to market faster and reduce SoC design and verification cost by applying best practices in RTL creation and functional verification
The Synopsys DesignWare® USB 2.0 picoPHY provides designers with a complete
physical (PHY) layer IP solution, designed for low power mobile and consumer
applications such as next-generation, feature-rich smartphones and mobile
internet devices. The DesignWare USB 2.0 picoPHY IP delivers smaller die area
(approximately 30%) and lower leakage power compared to current USB 2.0 PHY IP
products, for reduced silicon cost and longer battery life.
Optimized for mobile and consumer electronic applications, the DesignWare USB
2.0 picoPHY implements the latest Battery Charger (version 1.1) and USB On-The-
Go (OTG) version 2.0 specifications from the USB Implementer's Forum (USBIF).
Architected for the industry's most advanced 1.8V process technologies, the
USB 2.0 picoPHY is designed with features created to minimize effects due to
variations in foundry process, device models, package and board parasitics.
The DesignWare USB 2.0 picoPHY builds on years of customer success with Synopsys' silicon-proven USB 2.0 PHY IP product line, that has been successfully deployed in over 300 customer designs and over 50 process technologies ranging from 180 nm to 32 nm. When
combined with the DesignWare Host, Device or On-The-Go (OTG) digital controllers
and verification IP, the DesignWare USB 2.0 picoPHY delivers a complete low power
and small die area solution for advanced system-on-chip (SoC) designs.
