The DesignWare® Endpoint (EP) Cores for PCI Express® implements a configurable and scalable Endpoint interface for integration into ASICs and FPGAs providing designers with a high-quality IP that reduces risk and improves time-to-market. The silicon-proven DesignWare EP core is compliant to the latest PCI-SIG® and PIPE specifications and has been extensively validated with multiple HW platforms, PHYs and PCIe verification suites. As the industry standard for PCI Express, Synopsys offers a comprehensive IP solution that is in volume production and has been successfully implemented in a wide range of applications.
The synthesizable core integrates quickly and easily into SoC designs with a user-friendly application interface and conservative timing suitable for a wide range of ASIC and FPGA technologies. The core is available in your choice of datapath widths, PIPE interface widths, and operating frequencies for optimization of size, power, and throughput. DesignWare PCI Express cores are fully compliant with the PCI Express Base Specification 3.0, 2.0 and 1.1 and are used to power the industry's PCI Express compliance testing at PCI-SIG Compliance Workshops.
You can view all Synopsys PCI Express videos here.
DesignWare IP for PCI Express Complete Solution Datasheet DesignWare IP for PCI Express Endpoint Core Datasheet DesignWare IP for PCI Express Single Root I/O Virtualization Datasheet DesignWare IP for PCI Express to AMBA 2.0 AHB Bridge Datasheet DesignWare IP for PCI Express to AMBA 3 AXI Bridge Datasheet DesignWare Z-Core IP for PCI Express Datasheet *Japan Only*
DesignWare PCIe 3.0 at 8.0 GT/s
This demo showcases the benefits of the high-performance PCI Express® 3.0 interface operating at 8.0 GT/s. We show the performance throughput of a PC using an endpoint application designed with DesignWare® IP for PCI Express 3.0 and use a LeCroy Summit T3 Protocol Analyzer to verify compliance to the PCI Express 3.0 specification.
Torrey Lewis PCIe R&D
Designed according to the PCI Express 3.0, 2.0 and 1.1 specifications, including the latest errata
Supports PIPE PHY interface definition including variable clock and variable data
Supports 8.0, 5.0 and 2.5 Gbps line rates
Architecture supports x1, x2, x4, x8, and x16 lanes
Available in 32, 64, 128 and 256 bit data path widths for maximum flexibility
Optimal on-chip memory utilization and low latency
Bypass, cut-through and store-and-forward receive queues
Embedded DMA for increased performance
Legacy PCI, MSI and MSI-X interrupt support
Multi-function support
Full power management support
Advanced Error Reporting
ECC on the RAMs
Optional Parity on the datapath and RAM
Support for Single-Root I/O Virtualization (SR-IOV)
ASIC and FPGA support
Support for AMBA 3 AXI and AMBA AHB interfaces
PCI Express Endpoint - 128 Bit x16 STARs Subscribe
PCI Express Endpoint - 128 Bit x8 STARs Subscribe
PCI Express Endpoint - 32 Bit x1-x4 STARs Subscribe
PCI Express Endpoint - 64 Bit x1-x8 STARs Subscribe
PCI Express 1.0 Endpoint - 128 bit (x4,x8,x16), 256-bit (x8,x16) STARs Subscribe
PCI Express 1.0 Endpoint - 32 bit (x1,x4), 64-bit (x2,x4,x8) STARs Subscribe
PCI Express 2.0 Endpoint - 128 bit (x4,x8,x16), 256-bit (x8,x16) STARs Subscribe
PCI Express 2.0 Endpoint - 32 bit (x1,x4), 64-bit (x2,x4,x8) STARs Subscribe
PCI Express 3.0 Endpoint - 128 bit (x4,x8,x16), 256-bit (x8,x16) STARs Subscribe
PCI Express 3.0 Endpoint - 32 bit (x1,x2), 64-bit (x1,x2,x4) STARs Subscribe
PCI Express Endpoint - x1 LE STARs Subscribe
PCI Express Endpoint - x1 SE STARs Subscribe
Description
PCI Express 1.0 Endpoint - 128 bit (x4,x8,x16), 256-bit (x8,x16)
Name
dwc_pci_express_ep_gen1_128b_256b
Version
4.11a
STARs
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dw_iip_DWC_pcie_ep
Product Code
8789-0
Description
PCI Express 1.0 Endpoint - 32 bit (x1,x4), 64-bit (x2,x4,x8)
Name
dwc_pci_express_ep_gen1_32b_64b
Version
4.11a
STARs
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myDesignWare
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DesignWare Cores
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dw_iip_DWC_pcie_ep
Product Code
8788-0
Description
PCI Express 2.0 Endpoint - 128 bit (x4,x8,x16), 256-bit (x8,x16)
Name
dwc_pci_express_ep_gen2_128b_256b
Version
4.11a
STARs
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dw_iip_DWC_pcie_ep
Product Code
8797-0
Description
PCI Express 2.0 Endpoint - 32 bit (x1,x4), 64-bit (x2,x4,x8)
Name
dwc_pci_express_ep_gen2_32b_64b
Version
4.11a
STARs
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DesignWare Cores
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dw_iip_DWC_pcie_ep
Product Code
8796-0
Description
PCI Express 3.0 Endpoint - 128 bit (x4,x8,x16), 256-bit (x8,x16)
Name
dwc_pci_express_ep_gen3_128b_256b
Version
4.11a
STARs
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dw_iip_DWC_pcie_ep
Product Code
8805-0
Description
PCI Express 3.0 Endpoint - 32 bit (x1,x2), 64-bit (x1,x2,x4)
Name
dwc_pci_express_ep_gen3_32b_64b
Version
4.11a
STARs
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dw_iip_DWC_pcie_ep
Product Code
8804-0
Description
PCI Express Endpoint - 128 Bit x16
Name
dwc_pci_express_ep_128b_x16
Version
4.11a
STARs
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DesignWare Cores
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dw_iip_DWC_pcie_ep
Description
PCI Express Endpoint - 128 Bit x8
Name
dwc_pci_express_ep_128b_x8
Version
4.11a
STARs
Open and/or Closed STARs
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DesignWare Cores
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dw_iip_DWC_pcie_ep
Description
PCI Express Endpoint - 32 Bit x1-x4
Name
dwc_pci_express_ep_32b_x1-x4
Version
4.11a
STARs
Open and/or Closed STARs
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DesignWare Cores
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dw_iip_DWC_pcie_ep
Description
PCI Express Endpoint - 64 Bit x1-x8
Name
dwc_pci_express_ep_64b_x1-x8
Version
4.11a
STARs
Open and/or Closed STARs
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DesignWare Cores
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dw_iip_DWC_pcie_ep
Description
PCI Express Endpoint - x1 LE
Name
dwc_pci_express_ep_x1_le
Version
3.90a
STARs
Open and/or Closed STARs
myDesignWare
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DesignWare Cores
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dw_iip_DWC_pcie_ep_le
Description
PCI Express Endpoint - x1 SE
Name
dwc_pci_express_ep_x1_se
Version
3.90a
STARs
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dw_iip_DWC_pcie_ep_se