The DesignWare® Endpoint (EP) Controller IP for PCI Express® implements a configurable and scalable Endpoint interface for integration into ASICs and FPGAs providing designers with a high-quality IP that reduces risk and improves time-to-market. The silicon-proven DesignWare EP Controllers are compliant to the latest PCI-SIG® and PIPE specifications and have been extensively validated with multiple hardware platforms, PHYs and PCIe verification suites.
As the industry standard for PCI Express, Synopsys offers a comprehensive IP solution that is in volume production and has been successfully implemented in a wide range of applications.
The synthesizable controllers integrate quickly and easily into SoC designs with a user-friendly application interface and conservative timing suitable for a wide range of ASIC and FPGA technologies. The controllers are available in your choice of datapath widths, PIPE interface widths, and operating frequencies for optimization of size, power, and throughput. DesignWare Controller IP for PCI Express are fully compliant with the latest PCI Express Base Specifications and are used to power the industry's PCI Express compliance testing at PCI-SIG Compliance Workshops.
Prioritizing PCI Express 3.0 Bandwidth using DesignWare IP for PCIe High-performance I/O applications require moving multiple threads of data simultaneously. The DMA engine of the DesignWare IP for PCI Express 3.0 offloads SoC resources and maximizes the bandwidth of PCI Express 3.0 at 8.0 GT/s. This video showcases the ability of the DMA engine of the DesignWare® IP for PCI Express 3.0 to efficiently allocate bandwidth across multiple channels based on the application's requirements.