Virtual Prototyping
Accelerate pre-RTL embedded software development, hardware/software integration, and system validation
Architecture Design
Quickly explore tradeoffs in your SoC architecture to achieve optimal product performance and cost to avoid over- or under-design
FPGA-Based Prototyping
Accelerate the creation of your ASIC prototype with a high-speed hardware prototyping environment including a comprehensive software flow
Core Optimization
Differentiate your product with the right combination of performance, power and area for your most design-critical cores
Design Flow Deployment
Optimize your design flow to address the latest design challenges
Physical Design Assistance
Leverage our tape-out proven flows and project experience to implement your very-deep submicron chip
IP Integration & SoC Verification
Get to market faster and reduce SoC design and verification cost by applying best practices in RTL creation and functional verification
Synopsys XGMAC DesignWare® Core (DWC) is compliant with the IEEE 802.3ae specification. It interfaces to the PHY layer through the XGMII interface, and to the system through a FIFO interface. It is a highly configurable and eases SoC integration which allows it to tailor its feature set to the target application supporting speeds of 1G, 2.5G or 10G. The XGMAC can be integrated with the DWC Ethernet PCS and the DWC XAUI PHY cores from Synopsys to provide a complete 10 Gigabit Ethernet solution.DesignWare 10 Gigabit Ethernet IP Complete Solution Datasheet DesignWare XGMAC 10G Ethernet MAC Datasheet
