The DesignWare Universal DDR Protocol Controller (uPCTL) serves the memory control needs of applications with simple transactions that do not require an internal scheduler. The streamlined command based low-latency native interface (NIF) also enables the uPCTL to be integrated with a custom application specific scheduler.
The uPCTL is a bridge between a system-on-chip (SoC) application bus and a PHY for a DDR SDRAM, such as the Synopsys DesignWare DDR PHYs. The uPCTL and the DDR PHY together handle the details of the DDR protocol, allowing the application to access memory via simple on-chip bus read/write requests.
The uPCTL connects to DDR PHYs via a DFI 2.1 interface to create a complete memory interface and control solution. The controller includes software configuration registers, which are accessed through an AMBA 2.0 APB interface. DesignWare Universal DDR Memory and Protocol Controllers Datasheet
- For new designs or for designs with higher speed requirements and greater RAS features, consider Synopsys’s Enhanced Universal DDR Memory Controller (uMCTL2)
- Select a complete multi-ported enhanced Universal DDR Memory Controller offering up to 16 host ports, or join your own scheduler to a single-port enhanced Universal Memory Controller or Universal Protocol Controller
- Support for JEDEC standard DDR2, DDR3, LPDDR/Mobile DDR, LPDDR2 and LPDDR3 SDRAMs
- Compatible with all Synopsys DesignWare DDR PHYs (excluding DDR2/DDR PHYs)
- DFI 2.1 or DFI 3.1 compliant interface to DDR PHY (DFI 3.1 is backward compatible with DFI 2.1)
- Data rates up to 2133 Mbps in 1:2 frequency ratio, using a 533 MHz controller clock and 1066 MHz memory clock (dependent on process)
- Data rates up to 1600 Mbps in 1:1 frequency ratio, using a 800 MHz controller clock and 800 MHz memory clock (dependent on process)
|DDR Universal Protocol Controller (uPCTL) supporting DDR2, DDR3, Mobile DDR, LPDDR2, and LPDDR3||STARs||Subscribe|