The DesignWare DDR2/DDR PHYs are compiled into a hard macro that is optimized for specific foundry nodes. Each DDR2/DDR PHY is constructed from the following libraries of components: the application specific SSTL I/O library, a master and slave DLL library and Synopsys' unique Interface Timing Module (ITM) library composed of critical controller logic close to the I/Os. The ITMs facilitate the transition from double data rate to single data rate domains and eliminates timing closure issues between RTL-based Controller logic and the hard PHY IP. The DDR2/DDR PHY is assembled by direct cell abutment of the library components that eliminates the need for embedded clock distribution and critical signal timing matching.

DesignWare DDR2/DDR PHY Datasheet
 

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• When combined with a DesignWare DDR memory or protocol controller and verification IP, Synopsys provides a complete DDR2/DDR interface IP solution
• Scalable architecture that supports the full JEDEC speed range, from DDR-250 up to DDR2-1066
• Flexible, hardened macro approach: Three macro libraries are used to build the PHY, the application specific I/Os, Delay Locked Loops (DLLs) and Interface Timing Module (ITM) libraries
• All cells connect by direct abutment resulting in a complete PHY without any routing required - allows maximum flexibility to configure and place according to user requirements (data width, chip constraints, etc.), while simultaneously taking all the difficult timing closure out of the user's hands.
• Uses only 4 layers of metal for ITM & DLL
• Uses only 6 layers of metal for I/O cells
• Low latency
• Precision analog DLLs results in ultra low jitter
• Master DLL component for SDRAM command generation and general host timing
• Master/slave DLL component for SDRAM write data generation and read data capture
• Immune to PVT variation
• Uses core voltage level
• Optional DDR signal integrity service is available to assist customers with the integration of the PHY into their SoC, package and printed circuit board environments
• Real time DQS drift detection and compensation
• Configurable external data bus widths between 8 and 64 bits in 8-bit increments plus ECC
• Permits operating with DDR/DDR2 SDRAMs using data widths narrower than the compiled data width
• Low area and low power architecture
• Application specific DDR2/DDR I/O library featuring ODT and programmable drive strength (full, half drive) and includes power, analog, spacer, and corner cells.
• Area optimized I/O
• 40um I/O pitch for 130nm and 90nm
• 35um I/O pitch for 65nm
• Staggered I/O supported
• Supports CUP (Circuit Under Pad) and (Bond Over Active)
• Supports flip chip and wire bond (wire bond only in 130nm)
• Optional DDR signal integrity service is available to assist customers with the integration of the PHY into their SoC, package and printed circuit board environments

DDR2/DDR PHY - TSMC 130G33	STARs	Subscribe
DDR2/DDR PHY - TSMC 65GP25	STARs	Subscribe
DDR2/DDR PHY - TSMC 90G25	STARs	Subscribe
DDR2/DDR PHY - TSMC 90G33	STARs	Subscribe
DDR2/DDR PHY - UMC 90SP25	STARs	Subscribe

Description	DDR2/DDR PHY - TSMC 130G33
Name	dwc_ddr2_ddr_phy_tsmc130g33
Version	2.40b
STARs	Open and/or Closed STARs
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Product Type	DesignWare Cores
Documentation	Show Documents... Hide Documents... Databook DesignWare Cores DDR2/3-Lite SDRAM PHY Release Notes DesignWare Cores DDR2/1 SDRAM PHY
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Description	DDR2/DDR PHY - TSMC 65GP25
Name	dwc_ddr2_ddr_phy_tsmc65gp25
Version	1.60a
STARs	Open and/or Closed STARs
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Product Type	DesignWare Cores
Documentation	Show Documents... Hide Documents... Databook DesignWare Cores DDR2/DDR SDRAM PHY Implementation Guide DesignWare Cores DDR2/DDR SDRAM PHY Release Notes DesignWare Cores DDR2/DDR SDRAM PHY
Download	dwc_ddr2_ddr_phy_tsmc65gp25
Description	DDR2/DDR PHY - TSMC 90G25
Name	dwc_ddr2_ddr_phy_tsmc90g25
Version	1.80a
STARs	Open and/or Closed STARs
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Documentation	Show Documents... Hide Documents... Databook DesignWare Cores DDR2/DDR SDRAM PHY Release Notes DesignWare Cores DDR2/DDR SDRAM PHY
Download	dwc_ddr2_ddr_phy_tsmc90g25
Description	DDR2/DDR PHY - TSMC 90G33
Name	dwc_ddr2_ddr_phy_tsmc90g33
Version	1.80a
STARs	Open and/or Closed STARs
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Product Type	DesignWare Cores
Documentation	Show Documents... Hide Documents... Databook DesignWare Cores DDR2/DDR SDRAM PHY Release Notes DesignWare Cores DDR3-Lites DDR SDRAM PHY Release Notes
Download	dwc_ddr2_ddr_phy_tsmc90g33
Description	DDR2/DDR PHY - UMC 90SP25
Name	dwc_ddr2_ddr_phy_umc90sp25
Version	2.71a
STARs	Open and/or Closed STARs
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Product Type	DesignWare Cores
Documentation	Show Documents... Hide Documents... Databook DesignWare Cores DDR2/DDR SDRAM PHY Release Notes DesignWare Cores DDR2/DDR SDRAM PHY
Download	dwc_ddr2_ddr_phy_umc90sp25