Synopsys Consumer 8G PHY

The multiprotocol DesignWare Consumer 8G PHY IP, including PCI Express 3.1 and SATA 6G, is part of Synopsys’ high-performance multi-rate transceiver portfolio, meeting the growing needs for low-power consumption in battery-operated consumer and mobile applications. The Consumer 8G PHY delivers low active and standby power while exceeding signal integrity and jitter performance of the PCI Express 3.1 and SATA 6G standards.

The high-performance analog front-end incorporates advanced power saving features such as L1 sub-states in-conjunction with power gating in standby mode of operation. The hybrid transmit drivers support low power voltage mode and high swing current mode, with optional I/O supply under drive for low power in active mode of operation.

The PHY is small in area and provides a cost-effective solution. The PHY's Automatic Test Equipment (ATE) capabilities and optional wirebond packaging reduce the overall bill of materials (BOM) cost. The embedded bit error rate (BER) tester and internal eye monitor provide on-chip testability and visibility into channel performance. The PHY integrates seamlessly with the DesignWare Physical Sublayer IP and the digital controllers/media access controllers (MACs) to reduce design time and to help designers achieve first-pass silicon success. These features reduce both product development cycles and the need for costly field support.

Synopsys Consumer 8G PHY Datasheet
Synopsys SATA PHY Datasheet