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The DesignWare Verification IP (VIP) for PCI Express® provides a quick and efficient way to verify system-on-chip (SoC)designs with a PCI Express (PCIe)interface. The Synopsys VIP for PCI Express enables verification of PCI Express 3.0, 2.0 and 1.1 Endpoints,Switches, and Root Complex devices at the 8b/10b, PIPE or Serial interface.
The Synopsys VIP for PCI Express supports SystemVerilog and the Verification Methodology Manual(VMM). The VMM defines a coverage driven methodology for SystemVerilog using a constrained random environment. These features allow users to rapidly create complex protocol test scenarios for testing your SoC. It combines with the DesignWare digital IP core and PHY for PCI Express, to provide a complete solution for PCI Express designs.  DesignWare IP for PCI Express Complete Solution Datasheet
Verification IP for PCI Express Datasheet
- Supports PCI Express 3.0 (8GT/s), 2.0 (5.0GT/s) and 1.1 (GT/s)
- Supports x1, x2, x4, x8, x12, x16 lanes
- Supports Endpoints, Switches (Upstream and Downstream) and Root Complex devices
- Verification at PIPE, 10b, and serial interface
- Automatic handling of Transaction, Data Link, and Physical layer tasks
- Full Requester and Completer functions
- Automatic generation of flow control packets
- Built-in support for VMM, UVM, OVM and Verilog testbenches
- SystemVerilog, Verilog, VHDL and Vera® support
- Protocol checking and transaction logging
- Programmable error injection and detection
- Provides directed & constrained random traffic generation
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