Virtual Prototyping
Accelerate pre-RTL embedded software development, hardware/software integration, and system validation
Architecture Design
Quickly explore tradeoffs in your SoC architecture to achieve optimal product performance and cost to avoid over- or under-design
FPGA-Based Prototyping
Accelerate the creation of your ASIC prototype with a high-speed hardware prototyping environment including a comprehensive software flow
Core Optimization
Differentiate your product with the right combination of performance, power and area for your most design-critical cores
Design Flow Deployment
Optimize your design flow to address the latest design challenges
Physical Design Assistance
Leverage our tape-out proven flows and project experience to implement your very-deep submicron chip
IP Integration & SoC Verification
Get to market faster and reduce SoC design and verification cost by applying best practices in RTL creation and functional verification
Provides 100% functional coverage as defined in section 13 of the OCP 3.0 functional spec
Supports the full range of OCP configurations
Supports Multi-Threading and Bursts
Supports 2.1 tagging
Includes example system testbench with predefined test sequences and scenario generators to provide functional coverage of OCP 2.0/2.1/2.2 and 3.0
Supports randomized stimulus generation and configuration
Synopsys VIP for OCP is included with OCP-IP's CoreCreator and available to paid-up members of OCP-IP. For more information on OCP-IP membership please see the corporate introduction presentation on the OCP-IP website.
