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Synopsys' Verification IP (VIP) for ARM® AMBA® 3 Advanced eXtensible Interface (AXI™), provides a quick and efficient way to verify AMBA 3 AXI SoC designs by bringing advanced techniques for more productive verification. The AMBA 3 AXI protocol enhances the existing AMBA specification providing an infrastructure that has been designed to meet the needs of ultra-high-performance and complex system-on-chip (SoC) designs. Supporting register-sliced signaling and out-of-order burst transactions, the AMBA 3 AXI interface technology significantly improves intra-chip data transfers. The VIP for AMBA 3 AXI includes the following components: Master, Slave, Multiple Monitors, Interconnect for AMBA 3 AXI. DesignWare IP Solutions for the AMBA Interconnect
- Compliant with the latest AMBA 3 AXI specification
- Supports all AMBA 3 AXI data and address widths
- Supports all protocol transfer types and response types
- Supports constrained randomization of protocol attributes
- Checks for all protocol violations
- Logs transactions and reports on protocol violations and coverage
- Includes user-configurable message formatting
- Leverages Synopsys Discovery™ Verification Platform technology with full support for SystemVerilog, Vera®, Verilog and VHDL verification environments
- Includes protocol-based scenario generation
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