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The Verification IP (VIP) for the AMBA® interconnect provides a quick and efficient way to verify AMBA based SoC designs by bringing advanced techniques for more productive verification. In addition to a full featured command set for directed testing, the VIP for the AMBA interconnect provides constrained random test (CRT) generation, a powerful methodology that automatically generates transactions to stress the maximum number of protocol combinations. Constraints tell the models about the real world environment the chip needs to work in, and what makes sense for the design. The VIP for the AMBA interconnect monitors help determine when verification is complete. They track and log each transaction, provide coverage information, and give warnings and errors of protocol violations. DesignWare IP Solutions for the AMBA Interconnect
- Compliant with the AMBA 2.0 specification
- Supports all AMBA 2.0 data and address widths
- Supports all protocol transfer types and response types
- Supports AMBA, AMBA-Lite and multi-layer AHB
- Supports constrained randomization of protocol attributes
- Checks for protocol violations
- Logs transactions and reports on protocol coverage
- Includes user-configurable message formatting
- Written in OpenVera™ to leverage Synopsys Smart Verification technology with full support for VERA®, Verilog, VHDL and C verification environments
- Includes protocol-based scenario generation
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