Synopsys' DesignWare® ARC® EM6 processor core is based on the next-generation ARCv2 Instruction Set Architecture (ISA) and pipeline. With support for up to 32K of instruction and data cache, the DesignWare ARC EM6 core is optimized for use in embedded and deeply embedded applications that are power- and cost-sensitive such as memory cards, SSD controllers, power management, portable media players and other mobile devices.
The DesignWare ARCv2 architecture is a combined 16-/32-bit ISA that is compatible with the existing ARCv1 architecture used on the ARC 600 and 700 families. The ARCv2 ISA is implemented with a new scalable pipeline that enables the development of advanced RISC microprocessor cores with the optimum balance of performance, power consumption and size for a broad range of applications, giving designers a complete processor solution for their system-on-chip (SoC) designs.
The DesignWare ARC EM6 processor core supports separate instruction and data L1 cache memory spaces that can be independently configured for 2K, 4K, 8K, 16K or 32K size. The instruction and data cache can be set up by the user at build time to support 1-, 2- or 4-way set associativity, and a line size of 16, 32, 64 or 128 bytes. The caches can be individually configured to support line locking and invalidate, and to offer debug visibility.
The ARC EM6 has low-latency pipeline that is optimally balanced to deliver superior performance efficiency (DMIPS/mm2 and DMIPS/mW). The ARC EM6 processor core features native ARM® AMBA® AHB™, AHB-lite™ and BVCI interfaces to enable high system throughput. The core is fully supported by a complete suite of development tools, including the acclaimed MetaWare Development Kit that generates highly efficient code, the ARC simulators including xCAM and nSIM, and the ARChitect configuration tool.
A low-cost ARC EM Starter Kit enables designers to start early development of their designs. The EM Starter Kit, consisting of a hardware platform that includes pre-installed FPGA images of two ARC EM4 and two ARC EM6 configurations with peripherals and a software package, is a versatile platform for rapid
software development, code porting, software debugging, and system analysis of ARC
EM4 and EM6 processors.
Figure 1: DesignWare ARC EM6 Block Diagram
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Order the DesignWare ARC EM Starter Kit ($450 USD) DesignWare ARC EM6 Processor Datasheet
- Up to 32K instruction cache
- Up to 32K data cache
- 1.77 DMIPS/MHz performance, 3.41 CoreMarks/MHz
- Up to 240 interrupts with 16 levels
- 512B - 1MB instruction closely coupled memory (ICCM)
- 512B - 1MB data closely coupled memory (DCCM)
- Native ARM® AMBA® AHB™, AHB-lite™ and BVCI bus interfaces
- Optional 32x32 or 16x16 multipliers, or both
- Support for custom user extensions
*Measurements performed using Dhrystone v2.1, while following the procedure as outlined in the Dhrystone documentation.
CoreMark: 1.0 : 3.41 / MetaWare C/C++ Compiler I-2013.09 ccac -O -av2em -Xlib -Hmerge -Hinlsize=1000 -Hunroll=2,620 -Hsched_hybrid -Hall_sdata -Hloop_sms -Wcg,-max-predicate=0 / xCAM integrated model simulated @ 1 MHz
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