Synopsys' DesignWare® ARC® EM4 is based on the next-generation ARCv2 Instruction Set Architecture (ISA) and pipeline. At less than 10K gates, the core's small size makes it ideal for embedded and deeply embedded applications such as sensors and actuators, memory cards, SSD controllers, 8- and 16-bit microcontroller replacement and battery-operated products.
The DesignWare ARCv2 architecture is a combined 16-/32-bit ISA that is compatible with the existing ARCv1 architecture used on the ARC 600 and 700 families. The ARCv2 ISA is implemented with a new scalable pipeline that enables the development of advanced RISC microprocessor cores with the optimum balance of performance, power consumption and size for a broad range of applications, giving designers a complete processor solution for their system-on-chip (SoC) designs.
The DesignWare ARC EM4 processor core is designed to deliver unmatched performance efficiency (DMIPS/mm2 and DMIPS/mW). Its high degree of configurability enables design teams to optimize the ARC EM4 for a specific application's performance, power and size requirements.
The ARC EM4 features native ARM® AMBA® AHB™ and AHB-lite™, as well as BVCI interfaces to enable high system throughput. The core is fully supported by a complete suite of development tools, including the acclaimed MetaWare Development Kit that generates highly efficient code, the ARC simulators including xCAM and nSIM, and the ARChitect configuration tool.
A low-cost ARC EM Starter Kit enables designers to start early development of their designs. The EM Starter Kit, consisting of a hardware platform that includes pre-installed FPGA images of two ARC EM4 and two ARC EM6 configurations with peripherals and a software package, is a versatile platform for rapid
software development, code porting, software debugging, and system analysis of ARC
EM4 and EM6 processors.
Figure 1: DesignWare ARC EM4 Block Diagram
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Order the DesignWare ARC EM Starter Kit ($450 USD) DesignWare ARC EM4 Processor Datasheet
- Very small size - less than 10K gates
- 1.77 DMIPS/MHz performance, 3.41 CoreMarks/MHz*
- Up to 240 interrupts with 16 levels
- 512B - 1MB instruction closely coupled memory (ICCM)
- 512B - 1MB data closely coupled memory (DCCM)
- Native ARM® AMBA® AHB™, AHB-lite™ and BVCI bus interfaces
- Optional 32x32 or 16x16 multipliers, or both
- Support for custom user extensions
*Measurements performed using Dhrystone v2.1, while following the procedure as outlined in the Dhrystone documentation.
CoreMark: 1.0 : 3.41 / MetaWare C/C++ Compiler I-2013.09 ccac -O -av2em -Xlib -Hmerge -Hinlsize=1000 -Hunroll=2,620 -Hsched_hybrid -Hall_sdata -Hloop_sms -Wcg,-max-predicate=0 / xCAM integrated model simulated @ 1 MHz
|ARC EM4 32-bit processor core, ARC V2 ISA, for embedded applications||STARs||Subscribe|