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DesignWare ARC HS36 Processor

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The DesignWare® ARC® HS38 processor is a member of the high-speed 32-bit HS Processor Family and is optimized for use in high-performance embedded applications running Linux. The processor has a full-featured Memory Management Unit (MMU) supporting a 40-bit physical address space and page sizes up to 16 megabytes (MBs), giving designers the ability to directly address a terabyte of memory with faster data access and higher system performance. The HS38 has up to 64KB each of instruction and data cache, and is available in dual- and quad-core configurations with support for SMP Linux, full Level 1 cache coherency and up to 8 MB of Level 2 cache.

The HS38 is based on the highly-efficient ARCv2 instruction set architecture (ISA) and pipeline that deliver a high degree of performance efficiency and code density required for embedded applications. It is designed to be used in applications such as home routers and gateways, data centers, ADAS automotive systems, smart appliances, wearables, mobile devices and many other high-end embedded applications.

The ARC HS38 processor is highly configurable and enables designers to tailor each instance on their SoC for the optimum balance of performance, power and area. User-defined instructions that enable the integration of a user’s proprietary hardware accelerators allow for further optimization of the processors to dramatically improve application-specific performance while reducing power consumption.

To minimize system-level latency and increase overall system performance, the HS38 processor supports close coupled memories and direct mapping of peripherals, providing single-cycle access to other IP and memory blocks on the SoC. Native ARM® AMBA® AXI™ and AHB-Lite™ standard interfaces are configurable for 32-bit or 64-bit transactions to optimize throughput.

To facilitate rapid development of HS38-based solutions, the processor is supported by a complete suite of development tools, including the MetaWare Development Toolkit that generates highly efficient code, the ARC xCAM and nSIM simulators and the ARChitect configuration tool. In addition, Synopsys offers a suite of GNU tools (ARC GNU) for developers targeting the Linux operating system as well as bare metal systems. The ARC GNU Toolchain includes the GCC compiler and GDB debugger as well a number of utilities and libraries that make up a complete software toolchain. Linux for ARC processors (ARC Linux) allows software developers to leverage the large amount of Linux-compatible application software to quickly build complex systems for the HS38 with open source components. The HS38 processor is also supported by a robust ecosystem of third-party tools from leading industry vendors through the ARC Access Program.

DesignWare HS38 Block Diagram

DesignWare ARC HS36 Processor Datasheet
 

  • Instruction and data caches from 4KB to 64KB each
  • Achieves 3100 DMIPS at 1.6 GHz on 28HPM while consuming less than 60 mW of power (single core configuration, worst case silicon and conditions)
  • Delivers 1.93 DMIPS/MHz, 3.48 CoreMarks/MHz* (single core configuration)
  • Up to 1MB instruction and data close coupled memory (CCM)
  • 64-bit loads and stores
  • 64-bit multiply, multiply-accumulate
  • Radix-4 hardware divider
  • Optional IEEE 754-compliant floating point unit - single or double precision
  • Selectable ECC protection for all memories in the processor
  • Low-latency port for fast access to peripherals or memory
  • Up to 240 interrupts, with up to 16 configurable preemption levels
  • Native ARM® AMBA® AXI™, AHB™ interfaces
  • JTAG and Compact JTAG (cJTAG) debug interface
  • Optional real-time trace
  • Single-, dual- or quad-core configurations

    *Measurements performed using Dhrystone v2.1, while following the procedure as outlined in the Dhrystone documentation.
    CoreMark: 1.0 : 3.48 / MetaWare C/C++ Compiler I-2013.09 ccac -O -av2hs –Xlib -Xqmpyh -Xunaligned -Hmerge -Hinlsize=1200 -Hunroll=8,600 -Hsched_hybrid -Hall_sdata –Hccm -Hloop_sms -Wcg,-max-predicate=1 / xCAM integrated model simulated @ 1 MHz

ARC HS36 32-bit processor core, ARC V2 ISA, for embedded applicationsSTARsSubscribe

  Description ARC HS36 32-bit processor core, ARC V2 ISA, for embedded applications
  Name dwc_arc_hs36_core
  Version 1.0
  STARs Open and/or Closed STARs
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  Product Type DesignWare Cores
  Documentation
  Download arc_hs_processor
  Product Code 7849-0