The DesignWare® ARC® HS34 Processor is a member of the high-speed 32-bit HS Processor Family, optimized for use in high-end embedded applications where real-time, deterministic response is desired. The HS34 Processor can be configured as a dual- or quad-core for applications requiring multicore performance.
The HS34 Processor is based on the highly-efficient ARCv2 instruction set architecture (ISA), delivering a high degree of performance and code density with minimal power and area. These ARC processors are ideal for a variety of high-end embedded applications including SSD controllers, baseband control, digital TV, home networking, automotive systems, smart appliances, and many others.
Like all ARC processors, ARC HS34 Processors are highly configurable, enabling designers to tailor each instance on an SoC for the optimum balance of performance, power and area. The processors can be further optimized with user-defined instructions that enable the integration of a user’s proprietary hardware accelerators to dramatically improve application-specific performance while reducing power consumption.
To minimize system-level latency and increase overall system performance, the HS34 Processor supports close coupled memories and direct mapping of peripherals, providing single-cycle access to other IP and memory blocks on the SoC. Native ARM® AMBA® AXI™ and AHB™ standard interfaces are configurable for 32-bit or 64-bit transactions to optimize throughput.
The HS34 Processors are supported by a robust ecosystem of software and hardware development tools, including the MetaWare compiler/debugger, the nSIM instruction set simulator, the MQX real-time operating system (RTOS), and third-party tools, operating systems and middleware from leading industry vendors through the ARC Access Program.
Register for the ARC HS Processor Online Training DesignWare ARC HS34 Processor Datasheet
- Achieves 3100 DMIPS at 1.6 GHz on 28HPM while consuming less than 60 mW of power (single core configuration, worst case silicon and conditions)
- Delivers 1.93 DMIPS/MHz, 3.48 CoreMarks/MHz* (single core configuration)
- Up to 1MB instruction and data close coupled memory (CCM)
- 64-bit loads and stores
- 64-bit multiply, multiply-accumulate
- Radix-4 hardware divider
- Optional IEEE 754-compliant floating point unit - single or double precision
- Selectable ECC protection for all memories in the processor
- Low-latency port for fast access to peripherals or memory
- Up to 240 interrupts, with up to 16 configurable preemption levels
- Native ARM® AMBA® AXI™, AHB™ interfaces
- JTAG and Compact JTAG (cJTAG) debug interface
- Optional real-time trace
- Single-, dual- or quad-core configurations
*Measurements performed using Dhrystone v2.1, while following the procedure as outlined in the Dhrystone documentation.
CoreMark: 1.0 : 3.48 / MetaWare C/C++ Compiler I-2013.09 ccac -O -av2hs –Xlib -Xqmpyh -Xunaligned -Hmerge -Hinlsize=1200 -Hunroll=8,600 -Hsched_hybrid -Hall_sdata –Hccm -Hloop_sms -Wcg,-max-predicate=1 / xCAM integrated model simulated @ 1 MHz
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