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DesignWare ARC Floating Point Options for ARC Processors

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Power- and Area-Efficient Floating Point Unit for DesignWare ARC Processors
The DesignWare® ARC® Floating Point Units (FPU) option for ARC EM and ARC HS, processors adds performance efficient-single and double-precision hardware acceleration to enable floating point math acceleration. There are two versions of Floating Point Unit (FPU):

  • ARC FPU for EM – Supports ARC EM4, EM6 EM5D, EM7D and EM SEP
  • The ARC FPU for the EM processor family has full single-precision (SP) hardware support with double-precision (DP) acceleration extensions that speed up some of the more common double-precision operations, and is designed specifically to be compact in area and power to match the requirements for applications the ARC EM processors target.

  • ARC FPU for ARC HS – Supports the ARC HS34 and HS36 processor families
  • The ARC FPU for the HS processor family also has full single-precision hardware support but differentiates itself with more comprehensive double-precision support in the form of a much richer set of DP instructions, with full 64-bit data paths to and from HS core registers. All of the SP instructions in this FPU feature DP equivalents along with full DP to SP conversions. The HS FPU is also tailored to suit the 10-stage pipeline and high performance nature of the ARC HS processor cores.

Both FPUs are supported by the ARC MetaWare C/C++ Compiler and, when used together, both of the ARC FPUs comply with the IEEE-754-2008 Standard for Binary Floating Point Arithmetic.

Silicon-Efficient Floating Point Extensions for ARC Processors

Synopsys' ARC® FPX Floating Point Extensions add high-performance single- and double-precision math instructions to the ARC 600 and ARC 700 processor families. ARC FPX dramatically accelerates computations where data sets have a large dynamic range and when high precision is required.

When used with the ARC MetaWare compiler, DesignWare ARC FPX complies with the IEEE-754 Standard for Binary Floating Point Arithmetic. DesignWare ARC cores with DesignWare ARC FPX provide an ideal solution for system-on-chips (SoCs) that perform graphics and image processing, complex computations or control algorithms, especially where power and area budgets are constrained.

DesignWare ARC FPU and ARC FPX vs. Traditional Floating Point Coprocessor

  DesignWare ARC FPU (EM) DesignWare ARC FPU (HS) DesignWare ARC FPX Floating Point Coprocessor
Size in gates Single precision: 10 K - 14 K
Double precision: 27 K - 32 K*
Single precision: 10 K - 14 K
Double precision: 27 K - 45 K*
Single precision: 10 K - 13 K
Double precision: 26 K - 31 K*
Up to 100 K*
Performance (SP) Up to 1.0 Mflops / MHz Up to 1.0 Mflops / MHz Up to 1.0 Mflops / MHz Up to 1.3 Mflops / MHz
Power (SP) ~3 uW / MHz ** (40LP Process) ~3 uW / MHz ** (40LP Process) ~3 uW / MHz ** (40LP Process) 0.4 mW / MHz (130G Process)
Configurability options Flexible - SP, SP+DP or both Flexible - SP, DP or both Flexible - SP, DP or both None, monolithic design
Additional math instructions Yes, implemented by the user Yes, implemented by the user Yes, implemented by the user Fixed design, not extendible
* Gate count is estimated and will vary with process, cell library and speed of implementation
** Power is typical conditions and is estimated and will vary with process, cell library and speed of implementation

DesignWare ARC Floating Point Extensions Datasheet
DesignWare ARC Floating Point Unit for ARC EM Processors Datasheet
 

Very small die area and power
  • ARC FPU and FPX are both implemented using the APEX extensibility feature of the DesignWare ARC processor architectures
  • In contrast to the very large floating point co-processors required by other competitive cores, ARC FPX and FPU instructions are integrated into the ARC cores themselves at build time
  • Synopsys' approach achieves similar floating point performance to a co-processor, but with much smaller die area and power
Flexible configuration options
  • SoC designers can specify single precision extensions, double precision or both, as required in their application
Compiler math library optimizes performance
  • The ARC MetaWare compiler takes full advantage of the DesignWare ARC FPX and FPU instructions to accelerate transcendental and other functions specified in IEEE-754
FPU (ARC EM Family)
  • IEEE 754-2008 compliant
  • Full hardware single-precision support with double-precision acceleration
  • Full hardware single-precision (SP) and double-precision (DP) support (FPU for HS only)
  • Support for float-to-integer and integer-to-float conversion
  • Full support for SP to DP conversion (FPU for HS only)
  • Full 64-bit data paths to and from core registers (FPU for HS only)
  • Full clock-gating support for power efficiency
  • Power save features on all data paths and intermediate registers
  • Optional divide and square root support
  • Optional fused multiply/add and multiply/subtract
  • Single-cycle multiplier with two-cycle multiply option for higher frequency operation
  • Fewer than 14K gates in a single-precision, area-optimized configuration
  • Peak performance 1.0 Mflops / MHz
FPX (ARC 600 and ARC 700 Families)
  • Single Precision
    • MUL, ADD, SUB implemented directly in hardware
    • 3 CPU cycles latency per instruction, pipelined
    • 13 – 23x faster than an optimized software library
    • Peak performance 1.0 Mflops / MHz
    • Approx. 10 - 20K gates
  • Double Precision
    • MUL, ADD, SUB implemented directly in hardware
    • 5 CPU cycles per ADD or SUB instruction, 7 CPU cycles per MUL instruction
    • 9X - 19X faster than optimized software library
    • Peak performance: 200 Kflops / MHz
    • Approx. 25K - 30K gates
  • ARC MetaWare Math Library for FPU and FPX
    • Optimized for DesignWare ARC FPX and FPU hardware
    • Provides additional arithmetic and transcendental functions
    • Complies with IEEE-754
    • Allows re-linking of existing object files
IEEE754 compliant single and/or double precision floating point unit for ARC EM processor cores.STARsSubscribe
ARC FPX, optional Floating Point Unit, with single precision, double precision or bothSTARsSubscribe

  Description ARC FPX, optional Floating Point Unit, with single precision, double precision or both
  Name dwc_arc_fpx
  Version 2.2.5
  STARs Open and/or Closed STARs
  myDesignWare Subscribe for Notifications
  Product Type DesignWare Cores
  Documentation
  Download arc_ARC_FPX
  Product Code 8032-0
  
  Description IEEE754 compliant single and/or double precision floating point unit for ARC EM processor cores.
  Name dwc_arc_fpu
  Version 1.0
  STARs Open and/or Closed STARs
  myDesignWare Subscribe for Notifications
  Product Type DesignWare Cores
  Documentation
  Product Code A630-0