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Virtualize Your Connectivity IP with DesignWare System-Level Library

Frank Schirrmeister, Director of Marketing, System-Level Libraries

Building on the success of Synopsys' market leadership in connectivity IP of popular protocols, the DesignWare® System-Level Library mirrors the availability of implementation blocks at the system-level to allow efficient re-use in virtual platforms for pre-silicon embedded software development (also checkout our new whitepaper here). This virtualization of Synopsys' popular DesignWare Core IP titles is especially effective for pre-silicon development of drivers and firmware for protocols like USB, DDR, SATA and Ethernet.

The target application domain generally determines the required protocol interfaces for a chip design. For example, to be successful in mobile multimedia applications, chip designers typically need a feature phone protocol support for USB 2.0, USB 2.0 LPM, USB HSIC and SD/MMC interfaces.


Figure 1: Portfolio of Protocol IP in DesignWare® Implementation and System-Level IP

Figure 1 indicates the protocol support in Implementation IP together with the corresponding support in the System-Level Library.

A large number of protocol system-level models are already synchronized with the implementation IP available as DesignWare Cores. This means that the register images are an exact match between the two different levels of abstraction, which is ideal for developing driver software on a virtual platform accessing this IP. Some protocols like DDR and Firewire IEEE 1394 are available in the System-Level Library, but in a more general form and can be customized to specific implementations.

The coordinated availability of IP at the system-level makes it easy to develop, analyze and deploy virtual platforms which use Synopsys IP. Figure 2 illustrates a generic chip with signal level implementation IP, verification IP bridging from signal to transaction-level, and system-level IP at the transaction-level. The bottom portion of Figure 2 shows a generic block diagram with protocol blocks, busses and processors at the signal level, from which the DesignWare Cores can be implemented. The Verification IP is available for verification of protocols and can also be utilized to drive signals based on transaction input. The top portion shows the corresponding block diagram at the transaction-level as it is simulated using SystemC. TLM-2.0 in Synopsys Innovator as virtual platforms. At that level of abstraction, connections to real world I/O of USB, Ethernet, SATA and PCI, as well as skins and virtual representation of the actual device can be used to interact with the virtual platform.


Figure 2: Implementation, Verification and System-Level IP

The DesignWare System-Level Library's support of models with virtual I/O capabilities, allows the simulation model to directly connect to the host on which the virtual platform simulation executes. This enables unique debugging capabilities when, for example, connecting a virtual model of a media-player via USB to the host and interacting with it as if the real device would be plugged in.

The synchronized availability of implementation and SystemC TLM-2.0 system-level IP makes DesignWare System-Level Library the preferred source of models to accelerate the development of virtual platforms for pre-silicon software development.

For more information on DesignWare System-Level Library, please visit us here

For more information on Virtual Platforms for Early Software Development, please check out our whitepaper here.