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Synopsys DesignWare Verification IP Supports PCI Express Gen II and PIPE 1.87 Specifications

Synopsys has updated the DesignWare Verification IP to support the latest PCI Express Gen 2 and PIPE 1.87 Specifications. While maintaining backward compatibility with the 1.1 version of the specification, the Gen II specification increases the data rate from 2.5 to 5.0 gigabits per second to address the industry's need for increased bandwidth in networking, embedded and computer applications. The DesignWare Verification IP for PCI Express verifies all configurations of the digital core and compliance to the PCI Express compliance checklist. The DesignWare Verification IP supports the SystemVerilog design language and the Verification Methodology Manual (VMM). The VMM defines a coverage driven methodology for SystemVerilog using a constrained random environment. The Verification IP easily integrates in to Vera, Native Testbench, Verilog and VHDL testbenches.

For more information or to download the DesignWare Verification IP for PCI Express, visit http://www.synopsys.com/IP/InterfaceIP/PCIExpress