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Power Electronic Systems Simulate and execute behavioral design, modeling, and simulation for power electronics, multi-domain systems, and wire harnesses		System-Level Models Reduce risk and speed time to market with pre-verified models supporting industry standards for interoperability

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New DesignWare OCP Verification IP 3.0 Features

Synopsys has released a new version of the DesignWare® Verification IP (VIP) which offers added support for OCP 3.0 features including:

Reordering of responses to transactions with overlapping addresses: the Verification IP supports both types of response behavior
New posting semantics: WRNP and WRC transactions are legal when writeresp_enable is set to 0
Connect/Disconnect support: this feature defines a connection state negotiation protocol between a Master and Slave to support power management transitions.

The DesignWare VIP for OCP includes support for SystemVerilog-based, constrained random verification using a VMM object interface and provides coverage bins as defined in the OCP-IP specification and support for Verilog testbenches through a procedural command-based interface.

New intermediate and advanced VMM examples and QuickStart HTML-based documents offered in this release, helps users to quickly get up to speed with the DesignWare VIP for OCP in a VMM testbench environment. The release can be downloaded now at www.synopsys.com/VIP.

The DesignWare VIP for OCP is also included in CoreCreatorII which is available at no charge to members of the OCP-IP organization and can be requested from the OCP-IP website at www.ocpip.org.

Membership to the OCP-IP organization includes many benefits which can be viewed at http://www.ocpip.org/uploads/documents/OCP-IP_Value_Proposition_09_FINAL.new.pdf