DesignWare Verification IP adds support for SystemVerilog and VMM in VCS-MX
The latest release of VCS-MX adds support for DesignWare Verification IP with SystemVerilog and VMM. VMM is the Verification Methodology Manual for SystemVerilog co-authored by Synopsys and ARM. This release allows SystemVerilog-based VMM testbenches to be used with DesignWare verification IP in the verification of VHDL and mixed Verilog/VHDL designs. Available now is verification IP for AMBA AXI, AMBA 3 APB, AMBA 2.0 AHB, AMBA 2.0 APB, OCP 2.1, PCI Express, Ethernet 10/100/1G/10G, XAUII, USB 1.1, USB 2.0, USB OTG, and Serial IO. Contact your local Synopsys office regarding availability of Serial ATA and I2C verification IP.