By Design Phase


System-Level Design High-level block design, architecture design, virtual and FPGA-based prototyping, and, power electronics and wiring harness solutions		Manufacturing Mask synthesis and data prep, lithography simulation and verification and yield management

Verification High-performance system, RTL, debug, equivalence checking, mixed-signal verification solutions, and Verification IP		TCAD Process and device simulation solutions for technology development and manufacturing

Implementation & Sign-Off Advanced digital and custom IC and FPGA design solutions, including synthesis, physical implementation, physical verification, test and sign-off		Optical Solutions Optical solutions and analysis software and engineering services All Tools Directory of all Synopsys tools

Reduce Risk with High Quality IP


Interface IP Standard interfaces for SoC designs such as USB, PCIe, DDR, SATA, HDMI, MIPI, Ethernet and more		Processor IP ARC processor cores and extensions, ARC audio, and ARC development tools, operating systems & ecosystem

Analog IP Analog IP such as audio analog codecs, data converters and video analog front-end		SoC Infrastructure IP minPower Components, Verification IP and the DesignWare Library including datapath IP, AMBA, foundry libraries and 8-bit microcontrollers

Memories and Logic Libraries Logic libraries, memory compilers and non-volatile memories optimized for performance, power and area. Memory test and repair for higher test quality & yield		IP Subsystems Pre-verified audio subsystem integrating hardware, software and prototyping

Unmatched productivity from System to Implementation


High-Level Block Design Rapidly create and optimize differentiated IP blocks with Algorithm Design and Analysis, High-Level Synthesis, and Processor Development		Virtual Prototyping Accelerate pre-RTL embedded software development, hardware/software integration, and system validation

Architecture Design Quickly explore tradeoffs in your SoC architecture to achieve optimal product performance and cost to avoid over- or under-design		FPGA-Based Prototyping Accelerate the creation of your ASIC prototype with a high-speed hardware prototyping environment including a comprehensive software flow

Power Electronic Systems Simulate and execute behavioral design, modeling, and simulation for power electronics, multi-domain systems, and wire harnesses		System-Level Models Reduce risk and speed time to market with pre-verified models supporting industry standards for interoperability

Helping You Solve Your Toughest IC Design Challenges


Tools & Methodology Consulting Take advantage of the latest Synopsys tool features and methodologies		Core Optimization Differentiate your product with the right combination of performance, power and area for your most design-critical cores

Design Flow Deployment Optimize your design flow to address the latest design challenges		Physical Design Assistance Leverage our tape-out proven flows and project experience to implement your very-deep submicron chip

IP Integration & SoC Verification Get to market faster and reduce SoC design and verification cost by applying best practices in RTL creation and functional verification		FPGA-based Prototyping Improve time-to-market and avoid costly re-spins

Solutions for Semiconductor and System Design


End-to-End Solutions Comprehensive solutions: Advanced Low Power Solution, System-to-Silicon (S2S) Verification Solution, 3D-IC Design Solutions		Technical Platforms Integrated product platforms: Discovery Verification Platform, FPGA Design Solution, Galaxy Implementation Platform

Industry Solutions Tailored solutions for automotive, memory, mil/aero, mobile devices, & end-product categories		Lynx Design System A highly integrated, production-ready IC development platform

Expert Training and Support Services


Training Training courses on Synopsys' tools and methodologies		Global Support Centers Open a support issue online

SolvNet Get instant online access to the self-help support resources you need		Licensing, Installation & Compute Platforms The latest information about how to install, upgrade and manage your Synopsys licenses

Explore, Interact and Collaborate


Synopsys Users Group (SNUG) Technology users and product experts exchange ideas at SNUG conferences		University Program Resources for teaching IC design: how to apply to our program, curriculum, articles, support and training, and much more

Partners Collaborating to provide advanced reference flows, design kits, libraries, IP and methodology		Interoperability EDA tools working together for customer satisfaction and success

Blogs & Forums Insights from the experts, open forums for global Synopsys community		Conversation Central Podcast Where technology and business experts in the electronics industry come to talk.

Synopsys: Accelerating Innovation


About Synopsys Discover our company, our management team and our values		Synopsys Careers Learn about jobs, internships and our commitment to diversity

News Room Read Synopsys news, contact the PR team, download an image, or gather other information		Events Meet with Synopsys at an industry event, participate at a SNUG® conference, or attend a Synopsys workshop or seminar

Investor Relations Browse information for shareholders, analysts and potential investors		Community Involvement Strengthening our local communities

HOME

TECHNICAL BULLETIN

ARTICLE ARCHIVES

ARTICLE

DesignWare Technical Bulletin Article

Search Tools

Analog IP Selector

Memory & Logic IP Selector

Latest Update to DesignWare Documentation and STARS-on-the-web

DesignWare Documentation Updates for Q2 2007

Documentation for DesignWare products is continuously updated and released. In the months of February through April 2007, there were over 27,000 pages of documentation released with new or updated products.

When you download and install a DesignWare product, the associated documentation is always installed on your local network along with the product. In addition to your personal copy of the documentation, you can also check the Synopsys website for updates to the documentation you already have:
o DesignWare Library documentation
o DesignWare Cores documentation (requires SolvNet ID)

Usually, substantive updates to the documentation only accompany new product releases. If you want to be sure that you are information about new product releases, go to www.myDesignWare.com and register for updates to the products of interest. A SolvNet ID is required to access myDesignWare.com.

The tech pubs team is always welcomes your feedback. If you have questions or comments about DesignWare product documentation, please send to jonw@synopsys.com.

Recent Improvements to STARs on the Web

STARs on the Web is an online service available to DesignWare customers that allows you to see new problem problem reports (STARs) almost as soon as they are identified by Synopsys. STARs on the Web also displays planned enhancements, implemented enhancements, as well as a record of fixed problems for previous releases over the past two years.

STARs on the Web now features an improved presentation that organizes fixed STARs according to release number as well as a dynamic list of open STARs (discovered since the last release). Each tabbed page displays an expandable/collapsible list of STARs that contains STAR ID, severity level, and a brief description.

There have also been improvements to the information supplied in the individual STAR reports, although the types of improvements depend on the type of DesignWare product. Due to customer demand, an upcoming improvement to synthesizable IP products will be the addition of waveform graphics to better illustrate the problem and the fix.

If you are a DesignWare customer and have not yet viewed STARs on the Web for your product, go to www.designware.com and use the "Search for IP" box to find your product. Then click on the "STARs" link in the resulting search list. A SolvNet ID is required to view STARs on the Web.

If you have comments about STARs on the Web, please send to jonw@synopsys.com.

Improvements to Documentation for DesignWare Verification IP

As more of the DesignWare Verification IP products add RVM and VMM interfaces, it has been necessary to improve on the traditional methods of documenting reference material for those products. Rather than provide a collection of command reference pages, the most recent approach has been to use an open-source tool called Doxygen to generate robust HTML documentation directly from the OpenVera source code itself plus embedded comment text. The result is accurate and feature-rich HTML documentation that includes accurate class and member declarations, functions, and enumerations.

The home page of a Doxygen HTML features an expandable/collapsible bookmark list on the left side, and tabbed summary pages on the right side.

Individual class reference pages feature hyperlinked class hierarchy diagrams, class structure and contents, a class member index,
a navigation pane, and extensive hyperlinks to related members and classes. The result is documentation presented in familiar programming terms that provides quick navigation to overviews as well as details.

Availability of Doxygen HTML VIP Documentation

The following is a list of DesignWare Verification IP suites and the status of Doxygen HTML documentation for each suite.

AMBA (4.50a)
AHB: Fully commented Doxygen for both RVM and VMM
APB: None yet
AXI: Fully commented Doxygen for both RVM and VMM

Ethernet (4.00a)
- Fully commented Doxygen for both RVM and VMM

I2C (1.10b)
- Fully commented Doxygen for RVM and VMM will be in 2.00a

OCP (1.00b)
- Fully commented Doxygen for VMM (OpenVera RVM not supported)

PCI Express (5.90a)
- Uncommented Doxygen for both RVM and VMM
- Fully commented Doxygen for both RVM and VMM planned for Gen2 release

SATA (2.10a)
- Fully commented Doxygen for both RVM and VMM

SIO (1.40a)
- Uncommented Doxygen for both RVM and VMM
- Fully commented Doxygen will be available for the next release.

USB (4.50b)
- Fully commented Doxygen for both RVM and VMM