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Pipelining with DesignWare Building Block IP

Arshid Syed, Sr. CAE

DesignWare® Library has 166 Building Block IP. The DesignWare Library Datapath and Building Block IP are tightly integrated into Design Compiler (DC) and is part of the DC installation. It has a number of arithmetic, combinational, sequential, and floating point components, and many other blocks like FIFOs. The complete list of components is available at:

http://www.synopsys.com/dw/doc.php/doc/dwf/intro.pdf

This article provides a brief description of:

  • Manual pipeline insertion for combinational DesignWare Building Blocks
  • The new retiming feature for pipelined DesignWare Building Blocks

Manual pipeline insertion for combinational DesignWare Building Blocks

Manual pipelines can be inserted for combinational DesignWare Building Blocks such as floating point components, trigonometric components, etc.

The following example code shows the insertion of pipelines into a DesignWare Floating Point Divider (DW_fp_div). A sample script for synthesis is also provided. This script is based on methodology mentioned in the "RTL Coding Guidelines for Datapath", available at:

/dw/dwtb/pipelining/coding_guidelines.pdf

Example Instantiation for DesignWare Floating Point Component

module DW_fp_div_inst_pipe( inst_clk, inst_a, inst_b, inst_rnd, z_inst, status_inst );

parameter sig_width = 10;
parameter exp_width = 5;
parameter ieee_compliance = 0;
parameter inst_num_stages = 4;

input inst_clk;

input [sig_width+exp_width : 0] inst_a;
input [sig_width+exp_width : 0] inst_b;
input [2 : 0] inst_rnd;

output [sig_width+exp_width : 0] z_inst;
output [7 : 0] status_inst;

reg [sig_width+exp_width : 0] inst_a_reg;
reg [sig_width+exp_width : 0] inst_b_reg;

reg   [sig_width+exp_width : 0] z_inst_pipe1, z_inst_pipe2, z_inst_pipe3, z_inst_pipe4;
wire  [sig_width+exp_width : 0] z_inst_internal;

reg   [7 : 0] status_inst_pipe1, status_inst_pipe2, status_inst_pipe3, status_inst_pipe4;
wire  [7 : 0] status_inst_internal;

  // Instance of DW_fp_div
    DW_fp_div #(sig_width, exp_width, ieee_compliance) U1
                                                 (.a(inst_a_reg),
                                                  .b(inst_b_reg),
                                                  .rnd(inst_rnd),
                                                  .z(z_inst_internal),
                                                  .status(status_inst_internal)
								  );

  always @(posedge inst_clk) begin
    inst_a_reg <= inst_a;
    inst_b_reg <= inst_b;

//output to be registered by only allowing 5 pipeline stages to be moved

    z_inst_pipe1 <= z_inst_internal;
    z_inst_pipe2 <= z_inst_pipe1;
    z_inst_pipe3 <= z_inst_pipe2;
    z_inst_pipe4 <= z_inst_pipe3;

    status_inst_pipe1 <= status_inst_internal;
    status_inst_pipe2 <= status_inst_pipe1;
    status_inst_pipe3 <= status_inst_pipe2;
    status_inst_pipe4 <= status_inst_pipe3;

  end

 assign z_inst = (inst_num_stages==5) ? z_inst_pipe4:
                 (inst_num_stages==4) ? z_inst_pipe3:
                 (inst_num_stages==3) ? z_inst_pipe2:z_inst_pipe1;

 assign status_inst =(inst_num_stages==5) ? status_inst_pipe4:
                     (inst_num_stages==4) ? status_inst_pipe3:
                     (inst_num_stages==3) ? status_inst_pipe2:status_inst_pipe1;

endmodule

Recommended synthesis methodology for pipelined designs:

set target_library    "slow.db"
set link_library      "{*} $target_library"
set synthetic_library "dw_foundation.sldb"
set link_library [concat  $link_library $synthetic_library]
set search_path " .  \
./WORK/ \
/global/apps2/syn_2007.03-SP1/libraries/syn/ \
/libraries/synopsys/ \
"
define_design_lib WORK -path WORK
read_verilog ./DW_fp_div_inst_pipe.v

# First provide the loose constraints actual clock period multiplied by num_stages
# OR
# set_multicycle_path can also be used to account for the number pipeline stages 
# instead of adjusting the clock to account the number stages

set clk_per 5
create_clock [find port inst_clk] -period $clk_per
compile_ultra
set clk_per 1
create_clock [find port inst_clk] -period $clk_per
set_max_area 0
optimize_registers
compile -incr -map_effort high
report_qor
report_resources
report_timing
report_reference
report_cell
report_area
quit

The New Retiming Feature for Pipelined DesignWare Building Blocks:

Starting in 2007.03-SP1, for all pipelined DesignWare Building Blocks, bottom-up compilation or special user constraints (as mentioned in the above example) are not required. Designs with retiming attributes will be detected by "compile_ultra" and relaxed constraints (temporary constraints) will be set on the combinational logic of these designs until retiming happens to prevent over-optimization.

Usage: There is no user variable or command to control this feature. It is ON by default. Also, the optimize_registers command is not needed, since it is already used inside embedded scripts of pipelined DesignWare Building Blocks.

Advantages: Improvement in the synthesis results and ease of use.

Example Script to Use the New Retiming Feature:

#setup
analyze and elaborate pipelined DesignWare

#final design constraints
set clk_per 2
create_clock [find port inst_clk] -period $clk_per
compile_ultra
#reports
The following are the pipelined components with parameterizable pipeline stages, in which automatic pipeline retiming ensures optimal placement of pipeline registers:
DW_div_pipe               Stallable Pipelined Divider
DW02_mult_2_stage         Two-Stage Pipelined Multiplier
DW02_mult_3_stage         Three-Stage Pipelined Multiplier
DW02_mult_4_stage         Four-Stage Pipelined Multiplier
DW02_mult_5_stage         Five-Stage Pipelined Multiplier
DW02_mult_6_stage         Six-Stage Pipelined Multiplier
DW_mult_pipe              Stallable Pipelined Multiplier
DW_piped_mac              Pipelined Multiplier-Accumulator
DW_prod_sum_pipe          Stallable Pipelined Generalized Sum of Products
DW_sqrt_pipe              Stallable Pipelined Square Root