New Floating Point Components in DesignWare Library
The DesignWare® Library added 10 new Floating Point
components in the 2006.06 release. The DesignWare Library is
tightly integrated with Design Compiler (DC) and is part of a DC
installation. These components are available in the DesignWare
Library at no additional cost.
This article describes Floating Point components and their
features. It is assumed that the reader has a basic
knowledge of the floating-point number system.
Introduction
During the early days of digital computers a few decades ago,
the floating point capabilities were limited to scientific applications
and research. Now with the advancement of technology, high-end
applications such as 2D/3D Graphics, Digital Signal Processing (DSP), and
so on are part of our daily life. Floating Point operations play an
important role in graphics (such as geometric transformation of
coordinates, matrix calculation, vector operations, and so on) and in DSP
blocks (such as filters, FFT, and so on), apart from basic operations of addition,
subtraction, multiplication, division, and conversion (float to integer
and vice versa).
DesignWare Floating Point Component Features
Precision
IEEE-754 defines the standard for floating point arithmetic
operations. The basic floating point number format is single precision
(32-bit) and double precision (64-bit). As per the standard,
the floating point number is divided into three fields: sign,
significand, and exponent. The significand is also called the mantissa and
represents a fixed-point fractional value in the range [1, 2] with a
given number of fractional bits.
For example, a single-precision (32-bit) number is
divided as follows:
|
Sign |
8-bit Exponent |
23-bit Normalized Faction |
|
[31] |
[30-23] |
[22:0] |
- DesignWare Floating Point components are fully
parameterizable to IEEE formats, as well as to any custom format. For,
example half-precision (16 bits) is being used in many applications.
The range of supported exponents is between 3 and 31 bits, and the fractional
part can range from 2 to 253 bits. Higher precision gives a smaller
round-off error at the expense of a bigger circuit and more complexity.
Normalization
Normalization is the shifting of the mantissa to the left until
the value of the MSB is 1; for each bit shifted left, the exponent is
decreased by 1. So, for normalized numbers, the MSB is always 1 and
is always a hidden bit.
If the number is too small to be normalized (for example, in a
single precision when the exponent goes below -126), it is called
a denormal or sub-normal number. For denormal numbers, the exponent field
and the hidden bit are all zeros. Using denormals reduces loss of
accuracy in floating point numbers. IEEE supports denormals. During the
normalization process, when the exponent reaches the minimum value, the
mantissa is not shifted to the left anymore, and the exponent is set to
zero.
- DesignWare Floating Point components fully support
denormals. However, you can switch OFF the use of denormals by setting the
parameter ieee_compliance to “0”. Denormals are
considered as zeros with parameter ieee_compliance = 0.
Special Floating Point Numbers
Special numbers, such as +/- Zero, are represented
by the sign bit as 0 or 1 and both exponent and fraction parts as zeros.
Similarly, +/- Infinity is represented by the sign bit as 0 or 1, the
exponent field is all 1’s, and the fraction field is 0. Denormal numbers are
represented by the sign bit as 0 or 1 and the exponent field as all
0’s.
NaN (Not a Number) occurs in operations
such as 0/0. NaNs may have several valid representations, as far as the
exponent has a maximum value (all 1's) and the significand has a value
different than zero. When the DesignWare Floating Point components
generate NaNs, a significand value of 1
(00000…0001) is use. It is different from the representation of
infinity at the LSB only. However, the more general definition of NaNs
(non-zero significand and max exponent) is accepted for any input,
(including the representation that is used as output for the component.
- DesignWare Floating Point components fully support NaNs. As
mentioned earlier, you can switch OFF the use of NaNs by setting the
parameter ieee_compliance to “0”. NaNs are
considered as infinity with parameter ieee_compliance = 0.
Rounding
Rounding is the process by which a number
regarded as infinitely precise is mapped into a limited precision
Floating Point format. Supported rounding modes are:
- IEEE round to nearest (even)
- IEEE round to zero
- IEEE round to positive infinity
- IEEE round to negative infinity
- Round to nearest up
- Round away from zero
Status Flags
Depending upon the result, the component generates status
flags based on exceptions that occurred during any floating point
operation. The following are the status flags: Zero, Infinity, Invalid,
Tiny, Huge, Inexact, HugeInt, and Divide-by-0.
Multi-Operand Support
The important addition to the DesignWare Floating Point
Library is support for multi-operand addition. Floating point
addition is neither commutative nor associative, so the order of inputs
is important.
For example:
a + b + c ≠ c + b + a
and
(a + b) + c ≠ a + (b + c)
The multi-operand addition components are DW_fp_sum3 and
DW_fp_sum4.
- DW_fp_sum3 is a floating point component that is capable of
adding three floating point values (a, b, and c) in
order to produce a floating point result z. The final result is equivalent to the operation: (a + b) + c. The same operation can be done by using two floating point adders. However, the advantage of using multi-operand
components is that it is faster and more accurate than using two
floating point adders.
Similarly, addition of four FP values is
neither associative nor commutative. Thus, the order of inputs is
important to determine the actual output.
- DW_fp_sum4 is a floating point component that is capable of
adding four floating point values (a, b, c, and d) in
order to produce a floating point result z. The final result is equivalent to the
operation: ((a + b) + c) + d. This component is faster and more accurate than using three discrete floating point adders.
Formal Verification and Simulation Support
Floating Point arithmetic circuits are more
complex when compared with fixed-point or integer-arithmetic circuits.
This is due to the fact that, apart from simple arithmetic logic,
floating point components include packing, unpacking, alignment,
swapping, shifting, normalization, and rounding logic. Due to
the complexity of the floating point components, verification is a
difficult task. DesignWare Floating Point components support
formal verification with Formality and are fully verified with it;
there is no need for any new settings in the Formality flow.
Apart from formal verification, DesignWare Floating Point components
are extensively verified by making use of IEEE reference models.
For simulation purposes, Verilog and VHDL simulation models are also provided.
Accuracy Testing
DesignWare Floating Point components are extensively verified by:
- Making use of the IEEE reference model
- Simulating the test vectors generated by different CPUs
- Testing special cases such as overflow, underflow and normal/denormal boundary
- Random tests
Usage
DesignWare Floating Point components can be instantiated in both
VHDL and Verilog. For example:
Verilog:
DW_fp_add #(sig_width, exp_width, ieee_compliance)
U1 ( .a(inst_a), .b(inst_b), .rnd(inst_rnd), .z(z_inst),
.status(status_inst) );
VHDL:
library IEEE,DWARE;
use IEEE.std_logic_1164.all;
use DWARE.dw_foundation_comp.all;
-- Instance of DW_fp_add
U1 : DW_fp_add
generic map ( sig_width => inst_sig_width, exp_width => inst_exp_width,
ieee_compliance => inst_ieee_compliance)
port map ( a => inst_a, b => inst_b, rnd => inst_rnd, z => z_inst,
status => status_inst );
Synthesis Flow
Synthesis flow of DesignWare Floating Point components is
simple and straight-forward, since DesignWare is tightly integrated
with DC. The following is an example script:
set target_library "slow.db"
set link_library "{*} $target_library"
set synthetic_library "dw_foundation.sldb"
set link_library [concat $link_library $synthetic_library]
set search_path " . /DC/2006.06/libraries/syn/<lib_path>”
define_design_lib work -path ./work
read_verilog ./DW_fp_add_inst.v
set_max_delay -from [all_inputs] -to [all_outputs] 0
set_max_area 0
compile
compile -incr
write -f verilog -hier -o netlist.v
write -f ddc -hier -o netlist.ddc
report_qor
report_resources
report_timing
quit
Application Example
Multiply-Accumulate (MAC) is one of the common blocks of
DSP applications. The following is an example of MAC with a DesignWare Floating
Point multiplier and an adder.
Figure 1: MAC with DesignWare Floating
Point Multiplier and Adder
module MAC_example (clk, a, b, rnd, init, acc, status_add, status_mult);
parameter sig_width = 23;
parameter exp_width = 8;
parameter ieee_compliance = 1;
input [sig_width+exp_width : 0] a;
input [sig_width+exp_width : 0] b;
input [2 : 0] rnd;
input init;
input clk;
output [sig_width+exp_width : 0] acc;
output [7 : 0] status_add, status_mult;
wire [sig_width+exp_width : 0] z_mult;
wire [sig_width+exp_width : 0] acc_reg_in;
wire [sig_width+exp_width : 0] acc_in;
reg [sig_width+exp_width : 0] acc_reg_out;
DW_fp_mult #(sig_width, exp_width, ieee_compliance) U1 ( .a(a), .b(b),
.rnd(rnd), .z(z_mult), .status(status_mult) );
always @(posedge clk) begin
acc_reg_out <= acc_reg_in;
end
assign acc_in = acc_reg_out & init;
DW_fp_add #(sig_width, exp_width, ieee_compliance) U2
( .a(z_mult), .b(acc_in), .rnd(rnd), .z(acc_reg_in),
.status(status_add) );
assign acc = acc_reg_out;
endmodule
Backward Compatibility
DesignWare Floating Point components are a superset of Floating
Point components that are based on Module Compiler technology. To support the
old MC-based Floating Point components, the parameter
“ieee_compliance” should be set to
“0”.
Documentation and Download
For more information on DesignWare Floating Point components and their datasheets, use the following link:
http://www.synopsys.com/dw/doc.php/doc/dwf/datasheets/fp_overview2.pdf
DesignWare Floating Point components are already available with the 2006.06 image of Design Compiler.
If you are using an older version of Design Compiler (for example, 2005.09), please download the latest version of DesignWare Building Block IP:
http://www.synopsys.com/dw/buildingblock_dl.php
Summary
The new DesignWare Floating Point components are extensively verified and tested, and they full support the IEEE standard; they also support non-IEEE features with a parameter. These new Floating Point components take advantage of the DesignWare datapath generator technology that delivers better QoR than traditional technology. The DesignWare datapath generator is tightly integrated in DC and is supported by the Galaxy Design Platform.
When generating the datapath circuits, the generator takes into consideration the full timing context of the surrounding design and the characteristics of the technology library in order to generate hybrid datapath structures that are best fitted for the design target. The new floating point components not only save customer development effort, but they also deliver better QoR than many other alternatives, such as third-party IP.
Please see the following article for information on what's new in 2006.06 release of DesignWare Library:
http://www.synopsys.com/dw/dwtb.php?a=dwbb_0606
|
