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DesignWare Library 2010.03 Release

The 2010.03 release of the DesignWare® Library introduces new enhancements to its datapath generator and updates to some of the Building Block IP. This article provides a brief description and associated features of these new functions.

  • Support for Word-level Shifters in datapath generator

    This support enables expressions of word level shifters to be extracted into a bigger datapath block with surrounding datapath logic. This allows better datapath optimization and improves area QoR. To use this feature, the word shifting must be described in the RTL by a simple expression with constant multiplication. For example: assign z = a << (sh * word_size). This expression was previously implemented with an inferred shifter as a separate block. Starting in the 2010.03 release, the shifter can be extracted into a large datapath block with neighboring datapath logic.

  • Support for inverting full adders in datapath generator

    The adder tree in the carry-save adder (CSA) is currently built from standard (non-inverting) full-adders (FA) only. In the 2010.03 release, area-efficient adders can be implemented with the standard cell libraries that include full adder cells with inverted outputs. Synopsys has observed 4% to 12% area improvement in some test cases.

  • Enhacement to report_area and report_resources

    • report_resources:

      In the 2010.03 release, the report generated by the report_resources command is enhanced to include more specific optimization information. For extracted datapath blocks, the new Datapath Optimization Report will describe the Optimization Mode (area or speed) or Smartgen Option used on each block. For standalone operators (singletons), the Implementation Report will describe the optimization mode in the Implementation column of the report.

    • report_area:

      In the 2010.03 release, the command will have a '-designware' option. This new '-designware' option will give an estimated synthetic area of standalone operators (singletons) and extracted Datapath blocks (DP_OP).

  • Synplify support for DesignWare Building Block IP

    With the D-2010.03 release of Synplify Premier and DesignWare Building Blocks, designers can now use the same DesignWare Building Blocks in their Premier FPGA as they use in their Design Compiler synthesis flow. For more information on the usage and flow, visit:

    https://solvnet.synopsys.com/dow_retrieve/D-2009.12/synplify/user_guide.pdf