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New Datapath and Building Block IP in 2007.12 Release of the DesignWare Library

By Arshid Syed, DesignWare Sr. CAE

The DesignWare® Library introduced 10 new Building Block IP in 2007.12 release. The DesignWare Library Datapath and Building Block IP is tightly integrated with Design Compiler (DC) and is the part of the DC installation. This release contains new Floating Point Components, FIFO Controller and other combinational and arithmetic logic blocks. All of these components are available in the DesignWare Library at no additional cost.

This article provides a brief description and associated features of the new blocks.

Floating Point Components:

The following are the features the Floating Point Components:
  • The precision of the floating point numbers is parameterizable. These parameters cover all the IEEE formats.
  • The parameter range for exponents is from 3 to 31 bits.
  • Complete IEEE 754 compliance can be controlled with the ieee_compliance (=FALSE by default) parameter.
The following is the list of new DesignWare Floating Point Components added to the library:

DW_fp_macFloating Point Multiply-and-Add
DW_fp_exp2Floating Point Base-2 Exponential
DW_fp_log2Floating Point Base-2 Logarithm
DW_fp_recipFloating Point Reciprocal
DW_fp_sincosFloating Point Sine and Cosine Transform

For detail information on DesignWare Floating Point Components and its datasheets please go to the following link: http://www.synopsys.com/dw/doc.php/doc/dwf/datasheets/fp_overview2.pdf

DW_fp_mac: DW_fp_mac is a floating point component that performs the multiply and add operation. It multiplies inputs a and b and sums the result with input c (a*b + c) to produce a floating point multiply and add result, “z”.
The output of this component has accuracy consistent with the IEEE Standard 754, where the computation is done using infinite precision, and rounding performed as a last step to obtain the final result. So, the accuracy of DW_fp_mac is much better than the accuracy of a MAC implementation using DW_fp_mult and DW_fp_add. Also, DW_fp_mac is faster when compared with cascading individual DW_fp_mult and DW_fp_add components.

DW_fp_exp2: This component computes the Base-2 exponential of a floating-point input a, delivering an output z = (2a) that is also a floating-point value. Given the properties of algorithms to compute the exponential function, and the goal to have a component with good QoR, this component does not have rounding mode control as other FP components in the library. The output is bounded to have 1 ulp (unit in the least precision) error.

DW_fp_log2: This component computes the base-2 logarithm of a floating-point input a, delivering an output z that is also a floating-point value. Differently from other FP components, DW_fp_log2 does not have rounding mode control, given the properties of algorithms used to compute the logarithms and the goal to deliver the best possible QoR. The component is able to deliver outputs with 1 ulp error for most of the floating point range.

DW_fp_recip: DW_fp_recip is a floating point reciprocal component that calculates z = 1/a where a is a floating point value. DW_fp_recip supports the IEEE 754 compatible rounding modes as well as the faithful rounding that allows maximum 1 ulp error.

DW_fp_sincos: DW_fp_sincos is a floating point sine and cosine component that calculates z = sin (a), sin (π a), cos (a) or cos (π a) where a and z are floating point values. You choose the type of function by controlling the input sin_cos or setting the parameter pi_multiple. This component does not support rounding modes.

Digital Signal Processing (DSP)

Currently, different types of IIR and FIR are already available in the library. Two Dimensional Discreet Cosine Transform (DCT) is a new addition to the Digital Signal Processing group of DesignWare Building Blocks.

DW_dct_2d: This component can be used in a wide range of video and audio applications such as, Dolby Digital, NXN matrix for jpeg/mpeg, video telephony etc.

The DW_dct_2d implements the DCT. The device uses coefficients and data at the input port and generates the DCT data at the output.

In image processing, redundant information is contained in analog waves. In order to achieve reduction in data stream size, the transform attempts to remove as much of the redundancy as is possible. Transforms perform a perfect or lossless transformation of the data as spatial displacements into spatial frequencies. The inverse function reverses this transform and recovers the image data perfectly. The only loss involved in this transform is due to accuracy/truncation/rounding and another step outside of the transform called quantization.

Some of the features of DW_dct_2d:

  • Parameterized size of the two dimensional matrix to be transformed
  • Parameterized Coefficients (A-P) are the various DCT coefficients as calculated by the DCT formula
  • Support for both forward and reverse transform (idct_mode)
  • Supports signed and un-signed data types (tc_mode), for forward DCT mode.

Note: DW_dct_2d will be available in 2007.12-SP1 release.

Arithmetic and Combinational

The other arithmetic and combinational Building Block IPs added are:

DW_exp2Base-2 Exponential
DW_log2Base-2 Logarithm
DW_lzaLeading Zero Anticipator

DW_exp2: The DW_exp2 component takes an input a in fixed-point format and computes the function 2a. The input must be in the range (0,1) and therefore the output is in the range(1,2) (normalized). The number of bits used as input and output is defined by a parameter (op_width). The input has op_width fractional bits. The output has 1 integer bit (always 1) and op_width-1 fractional bits. The component implements the exponential function based on different algorithms for different ranges of precision. The selection of the algorithm is done automatically to deliver the best QoR.

DW_log2: DW_log2 computes the base-2 logarithm (log2) of an input a in fixed-point format. The input must be in the range (1,2) (normalized input) and therefore the output is in the range (0,1). The number of bits used as input and output is defined by a parameter (op_width). The input has 1 integer bit and op_width-1 fractional bits. The output has op_width fractional bits. The component implements the logarithm function using different algorithms depending on the number of input bits. The selection of the algorithm is done automatically to deliver the best QoR

DW_lza: The DW_lza takes as its input the normalized and swapped unsigned values to the subtraction. The inputs are designed to have a ≥ b and of the same width, and the output will be the number of most significant zeros anticipated to be in the result. This anticipated value may be off by one bit less than the true required shift. The shift count generated by this component, if in error, will be one less than the actual number of shifts required by the addition. The DW_lza is used to anticipate the number of bits required to shift in order to normalize the result of an addition. Conventional floating point addition requires the result to be normalized to a fixed radix point. Normalization shifts out the leading sign bits leaving a single bit adjacent to the radix point. Ordinary addition techniques wait until the final sum is obtained before determining the shift amount. In the normal floating point flow, the final determination of the shift can consume too much time, leading to a critical path. The DW_lza will do this calculation in parallel with the addition, allowing the design of higher performance adders.

Sequential Blocks

DW_pl_reg: This component is designed to make it easy to pipeline arbitrary logic or arithmetic structures using the register retiming features of Design Compiler (DC). It contains parameter controlled input and output registers which will stay in place at their respective block boundary - they are not allowed to be moved by DC's register retiming features.

  • Parameterized controlled width, logic states and input or output registers
  • Individual enables per register level
  • Automatically ungroups itself into its parent design for register retiming

Where to find 2007.12 DesignWare Building Blocks

For the complete list of DesignWare Building Block IP and their datasheets please visit

http://www.synopsys.com/dw/buildingblock.php

The new blocks are available with 2007.12 image of Design Compiler.

If you are using any older version of Design Compiler (2006.06 or later), you can still use the latest version DesignWare Building Blocks. Just download the DesignWare EST tar.gz file for your version of DC from the following page:

http://www.synopsys.com/dw/buildingblock_dl.php

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