A Guide to Understanding the Latest Enhancements for DesignWare Synthesizable IP for AMBA 3 AXI Interconnect Fabric
Synopsys, has released version 2007.08a of the DesignWare® synthesizable intellectual property (IP) for the ARM® AMBA 3 AXI™ protocol. The DesignWare IP solution for AMBA allows designers to easily integrate the high-speed protocol into their systems-on-chip (SoC) designs and enables designers of AMBA protocol-based systems to focus on the development of value-added elements to differentiate their products. The 2007.08a release includes performance enhancements to support higher frequencies for large AXI systems and implementation of new arbitration schemes to DesignWare interconnect fabric for AXI (DW_axi).
As part of the performance enhancement, the pipeline channel arbiter option has been added which gives the user another choice in pipelining each channel of the DW_axi.
Unlike the different timing modes available for DW_axi which pipelines between the master and slave port blocks, the user can select the pipeline channel arbiter ie. AXI_*_PL_ARB (*=AR,AW,R,W,B) parameter for each channel to add another pipelining stage after the channel arbiter.
When selected, this pipeline acts as another forward register-mode-only internal register slice; that is, the timing path has one buffer stage to ensure no throughput penalty. The user can select this pipelining stage standalone without selecting a full or forward register mode timing option, or it can be additional to a full or forward register mode timing option, giving a double pipelining of the channel. Note that each pipelining stage adds one cycle of latency through the channel.
Additional to the new pipelining stage, the existing pipelining stage has been architected in a way that results in gate count reduction. This new architecture brings about a 15% gate count reduction for comparable configurations.
Figure 1 illustrates where in the critical path the pipelining stage is added with these parameters in a channel that already has a forward register timing option selected.
Figure1: Timing Paths for Forward Registered Timing Mode with Pipeline Arbiter
With a forward register mode pipeline and arbiter pipeline stage enabled on each channel, a 13 master 14 slave DW_axi interconnect can synthesize to over 500 Mhz on a 90nm process. This result can be achieved with maximum master slave visibility, I/O delays of 20%,
slave interleaving depths of 1 and all other configuration parameters at their default values.
There are 3 new arbitration schemes that have been implemented for DW_axi that can be selected for each channel for every master and slave port.
Arbiter with First-Come-First-Served Priority Scheme - This arbitration scheme is a first-come-first-served priority scheme. In this scheme, on a cycle basis, the client that has been waiting the longest to be issued the grant, has the highest priority and the client has just been granted has the lowest priority. If two clients assert request input in the same cycle, the arbitration uses the index of inputs to break the tie among the requesting clients. For requests that are issued in the same cycle, the arbiter uses the index of the client to resolve the arbitration, with the lowest-numbered client winning. This is a fair arbitration scheme where each client is guaranteed to get a share of the available bandwidth.
Two-Tier Arbiter with Dynamic/Fair-Among-Equal Scheme - This arbitration scheme is a two-tiered arbitration scheme similar to the dynamic priority scheme (where the external priority of a client is used to decide the granted client) with the exception of arbitration of requesting clients of the same priority. In the first tier arbitration, the highest priority requesting client wins the arbitration. As before, the priority of each client can be statically configured via coreConsultant or dynamically configured via DW_axi inputs. But in cases where two or more clients of the arbiter have the same programmed priority value, the second-tier arbitration, based on fair-among-equal scheme, is used. In this scheme the grant is issued fairly, on a cycle by cycle basis for one cycle each, among actively requesting clients with same highest priority level.
In other words, this is a mixture of a fair arbitration scheme and a priority-based arbitration scheme. There is a fair sharing of available bandwidth between clients of the same priority, but the first tier of arbitration allows a higher-priority client to get immediate access.
User-Defined Arbitration Type - There is also an option to instantiate a plain text file called DW_axi_arb_user.v in the /src directory that the user can edit to add their own arbitration scheme. By default, the DW_axi_arb_user.v module instantiates a dynamic priority arbiter; this allows the packaged test environment to run through the coreConsultant GUI. The DW_axi_arb_user.v module is used wherever the User-Defined arbitration option is selected.
Refer to the databook for more details: http://www.synopsys.com/dw/doc.php/iip/DW_axi/latest/doc/dw_axi_db.pdf
The 2007.08a release of DesignWare synthesizable IP for AMBA 3 AXI protocol is available now at
DesignWare AMBA Solutions.
DesignWare Library licensees have access to this IP at no additional cost. RTL source code is available for license separately, on a pay-per-use basis.